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july 2003 the following document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. am49pdl127bh/ am49pdl129bh data sheet publication number 30452 revision a amendment +3 issue date december 16, 2003
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advance information this document contains information on a product under development at advanced micro devices. the information is intended to help you evaluate this product. amd reserves the right to change or discontinue work on this proposed product without notice. publication# 30452 rev: a amendment +3 issue date: december 16, 2003 refer to amd?s website (www.amd.com) for the latest information. am49pdl127bh/am49pdl129bh stacked multi-chip package (mcp) flash memory and psram 128 megabit (8 m x 16-bit) cmos 3.0 volt-only, simultaneous operation flash memory and 32 mbit (2 m x 16-bit) cmos pseudo static ram with page mode distinctive characteristics mcp features power supply voltage of 2.7 to 3.3 volt high performance ? access time as fast as 65 ns initial / 25 ns page package ? 73-ball fbga operating temperature ? ?40c to +85c flash memory features architectural advantages 128 mbit page mode device ? page size of 8 words: fast page read access from random locations within the page dual chip enable inputs (pdl129 only) ? two ce# inputs control selection of each half of the memory space single power supply operation ? full voltage range: 2.7 to 3.3 volt read, erase, and program operations for battery-powered applications simultaneous read/write operation ? data can be continuously read from one bank while executing erase/program functions in another bank ? zero latency switching from write to read operations flexbank architecture ? 4 separate banks, with up to two simultaneous operations per device ? bank a: 16 mbit (4 kw x 8 and 32 kw x 31) ? bank b: 48 mbit (32 kw x 96) ? bank c: 48 mbit (32 kw x 96) ? bank d: 16 mbit (4 kw x 8 and 32 kw x 31) secsi tm (secured silicon) sector region ? up to 128 words accessible through a command sequence ? up to 64 factory-locked words ? up to 64 customer-lockable words both top and bottom boot blocks in one device manufactured on 0.13 m process technology 20-year data retention at 125c minimum 1 million erase cycle guarantee per sector performance characteristics high performance ? page access times as fast as 25 ns ? random access times as fast as 65 ns power consumption (typical values at 10 mhz) ? 45 ma active read current ? 25 ma program/erase current ? 1 a typical standby mode current software features software command-set compatible with jedec 42.4 standard ? backward compatible with am29f and am29lv families cfi (common flash interface) complaint ? provides device-specific information to the system, allowing host software to easily reconfigure for different flash devices erase suspend / erase resume ? suspends an erase operation to allow read or program operations in other sectors of same bank unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences
2 am49pdl127bh/am49pdl129bh december 16, 2003 advance information hardware features ready/busy# pin (ry/by#) ? provides a hardware method of detecting program or erase cycle completion hardware reset pin (reset#) ? hardware method to reset the device to reading array data wp#/acc (write protect/acceleration) input ?at v il , hardware level protection for the first and last two 4k word sectors. ?at v ih , allows removal of sector protection ?at v hh , provides accelerated programming in a factory setting persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector ? sectors can be locked and unlocked in-system at v cc level password sector protection ? a sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password psram features power dissipation ? operating: 40 ma maximum ? standby: 70 a maximum ? deep power-down standby: 5 a ce1s# and ce2ps chip select power down features using ce1s# and ce2ps data retention supply voltage: 2.7 to 3.3 volt byte data control: lb#s (dq7?dq0), ub#s (dq15?dq8) 8-word page mode access
december 16, 2003 am49pdl127bh/am49pdl129bh 3 advance information general description the am29pdl127h/am29pdl129h are 128 mbit, 3.0 volt-only page mode and simultaneous read/write flash memory devices organized as 8 mwords. the word-wide data (x16) appears on dq15-dq0. the devices can be pro- grammed in-system or in standard eprom programmers. a 12.0 v v pp is not required for write or erase operations. the devices offer fast page access time of 25 and 30 ns, with corresponding random access times of 65 and 85 ns, respectively, allowing high speed microprocessors to oper- ate without wait states. to eliminate bus contention the de- vices have separate chip enable (ce#f1, ce#f2), write enable (we#) and output enable (oe#) controls. dual chip enables allow access to two 64 mbit partitions of the 128 mbit memory space. simultaneous read/write operation with zero latency the simultaneous read/write architecture provides simul- taneous operation by dividing the memory space into 4 banks, which can be considered to be four separate memory arrays as far as certain operations are concerned. the de- vice can improve overall system performance by allowing a host system to program or erase in one bank, then immedi- ately and simultaneously read from another bank with zero latency (with two simultaneous operations operating at any one time). this releases the system from waiting for the completion of a program or erase operation, greatly improv- ing system performance. the device can be organized in both top and bottom sector configurations. the banks are organized as follows: pdl127 configuration pdl129h configuration page mode features the page size is 8 words. after initial page access is accom- plished, the page mode operation provides fast read access speed of random locations within that page. standard flash memory features the device requires a single 3.0 volt power supply (2.7 v to 3.3 v) for both read and write functions. internally gener- ated and regulated voltages are provided for the program and erase operations. the device is entirely command set compatible with the jedec 42.4 single-power-supply flash standard . com- mands are written to the command register using standard microprocessor write timing. register contents serve as in- puts to an internal state-machine that controls the erase and programming circuitry. write cycles also internally latch ad- dresses and data needed for the programming and erase operations. reading data out of the device is similar to read- ing from other flash or eprom devices. device programming occurs by executing the program com- mand sequence. the unlock bypass mode facilitates faster programming times by requiring only two write cycles to pro- gram data instead of four. device erasure occurs by execut- ing the erase command sequence. the host system can detect whether a program or erase op- eration is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or ac- cept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data con- tents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc de- tector that automatically inhibits write operations during power transitions. the hardware sector protection feature disables both program and erase operations in any combina- tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. if a read is needed from the secsi sector area (one time pro- gram area) after an erase suspend, then the user must use the proper command sequence to enter and exit this region. the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode. power con- sumption is greatly reduced in both these modes. amd?s flash technology combined years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electri- cally erases all bits within a sector simultaneously via fowler-nordheim tunneling. the data is programmed using hot electron injection. chip enable control bank sectors ce#f1 a 16 mbit (4 kw x 8 and 32 kw x 31) b 48 mbit (32 kw x 96) c 48 mbit (32 kw x 96) d 16 mbit (4 kw x 8 and 32 kw x 31) chip enable control bank sectors ce#f1 a 16 mbit (4 kw x 8 and 32 kw x 31) b 48 mbit (32 kw x 96) ce#f2 c 48 mbit (32 kw x 96) d 16 mbit (4 kw x 8 and 32 kw x 31)
4 am49pdl127bh/am49pdl129bh december 16, 2003 advance information table of contents pdl127 configuration ........................................................... 3 pdl129h configuration ......................................................... 3 product selector guide . . . . . . . . . . . . . . . . . . . . . 6 mcp block diagram . . . . . . . . . . . . . . . . . . . . . . . . 6 connection diagram?pdl129 . . . . . . . . . . . . . . . . 7 special package handling instructions .................................... 7 connection diagram?pdl127 . . . . . . . . . . . . . . . . 8 special package handling instructions .................................... 8 look ahead ballout diagram . . . . . . . . . . . . . . . . 10 ordering information . . . . . . . . . . . . . . . . . . . . . . 12 mcp device bus operations . . . . . . . . . . . . . . . . 13 requirements for reading array data ................................... 15 random read (non-page read) ........................................ 15 page mode read ................................................................ 15 table 2. page select .......................................................................15 simultaneous operation ......................................................... 15 table 3. bank select (pdl129h) ....................................................15 table 4. bank select (pdl127h) ....................................................15 writing commands/command sequences ............................ 16 accelerated program operation .......................................... 16 autoselect functions ........................................................... 16 standby mode ........................................................................ 16 automatic sleep mode ........................................................... 16 reset#: hardware reset pin ............................................... 17 output disable mode .............................................................. 17 table 5. am29pdl127h sector architecture ..................................18 table 6. am29pdl129h sector architecture ..................................25 table 7. secsi tm sector addresses ................................................32 table 8. am29pdl127h boot sector/sector block addresses for pro- tection/unprotection ........................................................................33 table 9. am29pdl129h boot sector/sector block addresses for pro- tection/unprotection ........................................................................34 sector protection . . . . . . . . . . . . . . . . . . . . . . . . . 35 persistent sector protection ................................................... 35 persistent protection bit (ppb) ............................................ 35 persistent protection bit lock (ppb lock) .......................... 35 dynamic protection bit (dyb) ............................................. 35 table 10. sector protection schemes .............................................36 persistent sector protection mode locking bit ................... 36 password protection mode ..................................................... 36 password and password mode locking bit ........................ 37 64-bit password ................................................................... 37 write protect (wp#) ................................................................ 37 persistent protection bit lock .............................................. 37 high voltage sector protection .............................................. 38 figure 1. in-system sector protection/ sector unprotection algorithms ...................................................... 39 temporary sector unprotect .................................................. 40 figure 2. temporary sector unprotect operation........................... 40 secsi? (secured silicon) sector flash memory region ............................................................ 40 factory-locked area (64 words) ......................................... 40 customer-lockable area (64 words) ................................... 40 figure 3. pdl127h/129h secsi sector protection algorithm......... 41 secsi sector protection bits ................................................ 41 figure 4. secsi sector protect verify.............................................. 42 hardware data protection ...................................................... 42 low vcc write inhibit ......................................................... 42 write pulse ?glitch? protection ............................................ 42 logical inhibit ....................................................................... 42 power-up write inhibit ......................................................... 42 common flash memory interface (cfi) . . . . . . . 42 command definitions . . . . . . . . . . . . . . . . . . . . . 46 reading array data ................................................................ 46 reset command ..................................................................... 46 autoselect command sequence ............................................ 46 enter secsi? sector/exit secsi sector command sequence .............................................................. 47 word program command sequence ...................................... 47 unlock bypass command sequence .................................. 47 figure 5. program operation ......................................................... 48 chip erase command sequence ........................................... 48 sector erase command sequence ........................................ 48 figure 6. erase operation.............................................................. 49 erase suspend/erase resume commands ........................... 49 password program command ................................................ 49 password verify command .................................................... 50 password protection mode locking bit program command .. 50 persistent sector protection mode locking bit program com- mand ....................................................................................... 50 secsi sector protection bit program command .................... 50 ppb lock bit set command ................................................... 50 dyb write command ............................................................. 50 password unlock command .................................................. 50 ppb program command ........................................................ 51 all ppb erase command ........................................................ 51 dyb write command ............................................................. 51 ppb lock bit set command ................................................... 51 ppb status command ............................................................ 51 ppb lock bit status command .............................................. 51 sector protection status command ....................................... 51 command definitions tables .................................................. 52 table 15. memory array command definitions ............................. 52 table 16. sector protection command definitions ........................ 53 write operation status . . . . . . . . . . . . . . . . . . . . 54 dq7: data# polling ................................................................. 54 figure 7. data# polling algorithm .................................................. 54 ry/by#: ready/busy# ............................................................ 55 dq6: toggle bit i .................................................................... 55 figure 8. toggle bit algorithm........................................................ 55 dq2: toggle bit ii ................................................................... 56 reading toggle bits dq6/dq2 ............................................... 56 dq5: exceeded timing limits ................................................ 56 dq3: sector erase timer ....................................................... 56 table 17. write operation status ................................................... 57 absolute maximum ratings . . . . . . . . . . . . . . . . 58 figure 9. maximum negative overshoot waveform ...................... 58 figure 10. maximum positive overshoot waveform...................... 58 esd immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 59 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 11. test setup.................................................................... 61 figure 12. input waveforms and measurement levels ................. 61 psram ac characteristics . . . . . . . . . . . . . . . . . 62 ce#1ps timing ....................................................................... 62
december 16, 2003 am49pdl127bh/am49pdl129bh 5 advance information figure 13. timing diagram for alternating between pseudo sram and flash................................................. 62 flash ac characteristics . . . . . . . . . . . . . . . . . . . 63 read-only operations ? am29pdl127h ............................... 63 read-only operations ? am29pdl129h ............................... 63 figure 14. read operation timings ................................................ 64 figure 15. page read operation timings....................................... 64 hardware reset (reset#) .................................................... 65 figure 16. reset timings ................................................................ 65 erase and program operations .............................................. 66 figure 17. program operation timings........................................... 67 figure 18. accelerated program timing diagram........................... 67 figure 19. chip/sector erase operation timings ........................... 68 figure 20. back-to-back read/write cycle timings ....................... 69 figure 21. data# polling timings (during embedded algorithms).. 69 figure 22. toggle bit timings (during embedded algorithms)....... 70 figure 23. dq2 vs. dq6.................................................................. 70 temporary sector unprotect .................................................. 71 figure 24. temporary sector unprotect timing diagram ............... 71 figure 25. sector/sector block protect and unprotect timing diagram .............................................................. 72 alternate ce#f1 controlled erase and program operations .. 73 figure 26. flash alternate ce#f1 controlled write (erase/program) operation timings........................................................................... 74 psram ac characteristics . . . . . . . . . . . . . . . . . 75 read cycle ............................................................................. 75 figure 27. pseudo sram read cycle........................................... 75 figure 28. page read timing ........................................................ 76 write cycle ............................................................................. 77 figure 29. pseudo sram write cycle?we# control ................... 77 figure 30. pseudo sram write cycle?ce1#s control ................ 78 figure 31. pseudo sram write cycle? ub#s and lb#s control.................................................................. 79 erase and programming performance . . . . . . . 80 latchup characteristics . . . . . . . . . . . . . . . . . . . . 80 package pin capacitance. . . . . . . . . . . . . . . . . . . 80 flash data retention . . . . . . . . . . . . . . . . . . . . . . 80 psram data retention . . . . . . . . . . . . . . . . . . . . 81 psram power on and deep power down . . . . . 81 figure 32. deep power-down timing............................................. 81 figure 33. power-on timing........................................................... 81 psram address skew . . . . . . . . . . . . . . . . . . . . . 82 figure 34. read address skew ..................................................... 82 figure 35. write address skew...................................................... 82 physical dimensions . . . . . . . . . . . . . . . . . . . . . . 83 tla073?73-ball fine-pitch grid array 8 x 11.6 mm ............. 83 revision summary . . . . . . . . . . . . . . . . . . . . . . . . 84
6 am49pdl127bh/am49pdl129bh december 16, 2003 advance information product selector guide mcp block diagram part number am49pdl127bh/am49pdl129bh speed option standard voltage range: v cc = 2.7?3.3 v flash memory pseudo sram 66 85 66 85 max access time, ns 65 85 70 85 page access time, ns 25 30 30 35 ce#f1 access, ns 65 85 70 85 oe# access, ns 25 30 25 30 v ss v cc s reset# we# oe# ce1#ps lb#s ub#s wp#/acc ce2ps 32 mbit pseudo sram 128 mbit flash memory dq15 to dq0 dq15 to dq0 a20 to a0 (a22) a21 to a0 ce#f1 ry/by# a21 to a0 (a22 pdl127 only) dq15 to dq0 ce#f2 (pdl129 only)
december 16, 2003 am49pdl127bh/am49pdl129bh 7 advance information connection diagram?pdl129 special package handling instructions special handling is required for flash memory products in molded packages (bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f1 ce#1ps a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2ps a20 dq4 v cc ps nc a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 ce#f2 a16 nc v ss nc nc nc nc nc nc pseudo sram only shared flash only 73-ball fbga top view
8 am49pdl127bh/am49pdl129bh december 16, 2003 advance information connection diagram?pdl127 special package handling instructions special handling is required for flash memory products in molded packages (bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 c for prolonged periods of time. a1 b1 c1 f1 g1 l1 m1 d2 e2 f2 g2 h2 j2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 b5 c5 d5 e5 h5 j5 k5 l5 b6 c6 d6 e6 h6 j6 k6 l6 c7 d7 e7 f7 g7 h7 j7 k7 c8 d8 e8 f8 g8 h8 j8 k8 d9 e9 f9 g9 h9 j9 a10 b10 f10 g10 l10 m10 nc nc nc nc nc nc nc nc nc a3 a2 a1 a0 ce#f1 ce#1ps a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 nc wp#/acc reset# ry/by# dq3 v cc f dq11 nc we# ce2ps a20 dq4 v cc ps nc a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 nc dq15 dq7 dq14 a15 a21 a22 a16 nc v ss nc nc nc nc nc nc pseudo sram only shared flash only 73-ball fbga top view
december 16, 2003 am49pdl127bh/am49pdl129bh 9 advance information pin description a20?a0 = 21 address inputs (common) a21 = address inputs (flash) a22 = address input (pdl127 only) (flash) dq15?dq0 = 16 data inputs/outputs (common) ce#f1 = chip enable 1 (flash) ce#f2 = chip enable 2 (flash) (pdl 129 only) ce#1ps = chip enable 1 (psram) ce2ps = chip enable 2 (psram) oe# = output enable (common) we# = write enable (common) ry/by# = ready/busy output and open drain. when ry/by# = v ih , the device is ready to accept read operations and commands. when ry/by# = v ol , the device is either executing an em- bedded algorithm or the device is executing a hardware reset opera- tion. ub#s = upper byte control (psram) lb#s = lower byte control (psram) reset# = hardware reset pin, active low wp#/acc = write protect/acceleration input. when wp/acc#= v il , the highest and lowest two 4k-word sectors are write protected regardless of other sector protection configurations. when wp/acc#= v ih , these sector are unprotected unless the dyb or ppb is programmed. when wp/acc#= 12v, program and erase operations are accelerated. v cc f = flash 3.0 volt-only single power sup- ply (see product selector guide for speed options and voltage supply tolerances) v cc s = psram power supply v ss = device ground (common) nc = pin not connected internally logic symbol 21 16 dq15?dq0 a20?a0 ce#f1 oe# we# reset# ub#s ry/by# wp#/acc a21 lb#s ce#1ps ce2ps ce#f2 (pdl129 only) a22 (pdl127 only)
10 am49pdl127bh/am49pdl129bh december 16, 2003 advance information look ahead ballout diagram b1 n1 e2 f2 g2 h2 j2 k2 d3 e3 f3 g3 h3 j3 k3 l3 d4 e4 f4 g4 h4 j4 k4 l4 c5 d5 e5 f5 j5 k5 l5 m5 c6 d6 e6 f6 j6 k6 l6 m6 d7 e7 f7 g7 h7 j7 k7 l7 d8 e8 f8 g8 h8 j8 k8 l8 e9 f9 g9 h9 j9 k9 b10 n10 nc b2 c2 d2 nc avd# a1 nc a2 nc b9 nc nc a9 nc a10 nc wp# ce#2 v cc /v ccq nc a3 a2 a1 a0 ce#f1 a7 a6 a5 a4 v ss oe# dq0 dq8 lb# ub# a18 a17 dq1 dq9 dq10 dq2 l2 nc ce#f2 acc or wp#/acc reset# ry/by# dq3 v cc f dq11 v cc we# ce2 a20 dq4 g5 h5 g6 h6 ce#1 v cc a23 ce2 a25 or v ccq a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 c3 c4 c7 c8 v ss clk rst# clk a12 a13 a14 a24 dq15 dq7 dq14 a15 a21 c9 d9 ry/by# ce#1 a22 a16 cres or v cc f m2 m3 m4 m7 m8 m9 irq/a27 a26 nc v ccq v ccq nc v ss l9 n9 lock or wp#/acc nc nc p1 p10 n2 p2 p9 nc nc nc nc nc data storage 2nd ram 1st ram ce1# v cc legend fasl standard mcp packages 7.0 x 9.0 mm 8.0 x 10.0 mm 8.0 x 11.6 mm 9.0 x 12.0 mm note: the future ballouts shown in this diagram represent possible future products with densities up to 4 gbits of flash plus 4 gbits of sram. device combinations include nor flash plus sram, nor flash plus psram, and nor flash plus psram plus data storage. contact a sales representative for device specifications, planned production, and availability before designing in any future product.
december 16, 2003 am49pdl127bh/am49pdl129bh 11 advance information to provide customers with a migration path to higher densities, as well as the option of stacking more die in one package, the preceding diagram shows a look-ahead ballout that supports: nor flash and sram densities up to 4 gigabits nor flash and psram densities up to 4 gigabits nor flash and psram and data storage den- sities up to 4 gigabits the signal locations of the resultant mcp device are shown in the diagram. note that for different densities, the actual package outline may vary. however, any ballout in any mcp will be a subset of the ballout dia- gram shown. in some cases, there may be outrigger balls in loca- tions outside the grid shown. do not connect these outrigger balls to any signal. for further information re- garding the look-ahead ballout, contact the appropri- ate amd or fujitsu sales office.
12 am49pdl127bh/am49pdl129bh december 16, 2003 advance information ordering information the order number (valid combination) is formed by the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. am49pdl12 7 b h 66 i t tape and reel t = 7 inches s = 13 inches temperature range i = industrial (?40 c to +85 c) speed option see ?product selector guide? on page 5. process technology h = 0.13 m pseudo sram device density b = 32 mbits control pins 7 = 1 ce flash 9 = 2 ce flash amd device number/description am49pdl127bh/am49pdl129bh stacked multi-chip package (mcp) flash memory and psram 128 megabit (8 m x 16-bit) cmos 3.0 volt-onl y, simultaneous operation flash memory and 32 mbit (2 m x 16-bit) pseudo static ram with page mode valid combinations order number package marking am49pdl127bh66i t, s m490000028 am49pdl127bh85i t, s m490000029 am49pdl129bh66i t, s m490000030 am49pdl129bh85i t, s m490000031
december 16, 2003 am49pdl127bh/am49pdl129bh 13 advance information mcp device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory loca- tion. the register is a latch used to store the com- mands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state machine outputs dictate the function of the device. tables 1-2 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail.
14 am49pdl127bh/am49pdl129bh december 16, 2003 advance information table 1. device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 9.0 0.5 v, x = don?t care, sadd = flash sector address, a in = address in, d in = data in, d out = data out notes: 1. other operations except for those indicated in this column are inhibited. 2. do not apply ce#f1 or 2 = v il , ce#1ps = v il and ce2ps = v ih at the same time. 3. don?t care or open lb#s or ub#s. 4. if wp#/acc = v il , the boot sectors will be protected. if wp#/acc = v ih the boot sectors protection will be removed. if wp#/acc = v acc (9v), the program time will be reduced by 40%. 5. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector/sector block protection and unprotection? section. 6. if wp#/acc = v il , the two outermost boot sectors remain protected. if wp#/acc = v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection and unprotection?. if wp#/acc = v hh, all sectors will be unprotected. 7. data will be retained in psram. 8. data will be lost in psram. 9. both ce#f1 inputs may be held low for this operation. operation (notes 1, 2) ce#f1 active ce#f2 (pdl129 only) ce#1ps ce2ps oe# we# addr. lb#s (note 3) ub#s (note 3) reset# wp#/ acc (note 4) dq7? dq0 dq15? dq8 read from active flash (note 7) l (h) h (l) hh lh a in xx h l/h d out d out (note 8) h l write to active flash (note 7) l (h) h (l) hh hl a in xx h (note 4) d in d in (note 8) h l standby v cc 0.3 v hhxxx xx v cc 0.3 v h high-z high-z deep power-down standby v cc 0.3 v hlxxxxx v cc 0.3 v h high-z high-z output disable (note 9) l (h) h (l) l h hh x x x h l/h high-z high-z hh x x x flash hardware reset (note 7) x hh x x x x x l l/h high-z high-z (note 8) h l sector protect (notes 6, 10) (note 7) l (h) h (l) hh hl sadd, a6 = l, a1 = h, a0 = l xx v id l/h d in x (note 9) h l sector unprotect (notes 5, 9) (note 7) l (h) h (l) hh hl sadd, a6 = h, a1 = h, a0 = l xx v id (note 6) d in x (note 8) h l temporary sector unprotect (note 7) x hh xx x x x v id (note 6) d in high-z (note 8) h l read from psram h h l h l h a in ll hx d out d out h l high-z d out lh d out high-z write to psram h h l h x l a in ll hx d in d in h l high-z d in lh d in high-z
december 16, 2003 am49pdl127bh/am49pdl129bh 15 advance information requirements for reading array data to read array data from the outputs, the system must drive the oe# and appropriate ce#f1/ce#f2 (pdl129 only) pins to v il . ce#f1 and ce#f2 are the power con- trol and for pdl129 select the lower (ce#f1) or upper (ce#f2) halves of the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no com- mand is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. each bank remains enabled for read access until the command register contents are altered. refer to the flash ac characteristics table for timing specifications and to figure 14 for the timing diagram. i cc1 in the dc characteristics table represents the ac- tive current specification for reading array data. random read (non-page read) address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from the stable ad- dresses and stable ce#f1 to valid data at the output inputs. the output enable access time is the delay from the falling edge of the oe# to valid data at the output inputs (assuming the addresses have been sta- ble for at least t acc ?t oe time). page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read oper- ation. this mode provides faster read access speed for random locations within a page. address bits a22?a3 (a21?a3 for pdl129) select an 8-word page, and address bits a2?a0 select a specific word within that page. this is an asynchronous operation with the microprocessor supplying the specific word location. the random or initial page access is t acc or t ce and subsequent page read accesses (as long as the loca- tions specified by the microprocessor fall within that page) are t pac c . when ce#f1 and ce#f2 (pdl129 only) are deasserted (ce#f1=ce#f2=v ih ), the reasser- tion of ce#f1 or ce#f2 (pdl129 only) for subsequent access has access time of t acc or t ce . here again, ce#f1/ce#f2 (pdl129 only) selects the device and oe# is the output control and should be used to gate data to the output inputs if the device is selected. fast page mode accesses are obtained by keeping a22?a3 (a21?a3 for pdl129) constant and changing a2 to a0 to select the specific word within that page. table 2. page select simultaneous operation in addition to the conventional features (read, pro- gram, erase-suspend read, and erase-suspend pro- gram), the device is capable of reading data from one bank of memory while a program or erase operation is in progress in another bank of memory (simultaneous operation), the bank can be selected by bank ad- dresses (a22?a20) (a21?a20 for pdl129) with zero latency. the simultaneous operation can execute multi-func- tion mode in the same bank. table 3. bank select (pdl129h) table 4. bank select (pdl127h) word a2 a1 a0 word 0 000 word 1 001 word 2 010 word 3 011 word 4 100 word 5 101 word 6 110 word 7 111 bank ce#f1 ce#f2 a21?a20 bank a 0 1 00, 01, 10 bank b 0 1 11 bank c 1 0 00 bank d 1 0 01, 10, 11 bank a22?a20 bank a 000 bank b 001, 010, 011 bank c 100, 101, 110 bank d 111
16 am49pdl127bh/am49pdl129bh december 16, 2003 advance information writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce#f1 or ce#f2 (pdl 129 only) to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once a bank enters the un- lock bypass mode, only two write cycles are required to program a word, instead of four. the ?word pro- gram command sequence? section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. ta bl e 4 indicates the address space that each sector occupies. a ?bank address? is the address bits required to uniquely select a bank. similarly, a ?sector address? refers to the address bits required to uniquely select a sector. the ?command definitions? section has details on erasing a sector or the entire chip, or suspending/resuming the erase op- eration. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the flash ac characteristics section contains timing specifica- tion tables and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. this function is primarily in- tended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device auto- matically enters the aforementioned unlock bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. the system would use a two-cycle program command sequence as required by the unlock bypass mode. removing v hh from the wp#/acc pin returns the device to nor- mal operation. note that v hh must not be asserted on wp#/acc for operations other than accelerated pro- gramming, or device damage may result. in addition, the wp#/acc pin should be raised to v cc when not in use. that is, the wp#/acc pin should not be left float- ing or unconnected; inconsistent behavior of the de- vice may result. autoselect functions if the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on dq15?dq0. standard read cycle timings apply in this mode. refer to the autoselect command se- quence sections for more information. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce#f1, ce#f2 (pdl129 only) and reset# pins are all held at v io 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce#f1, ce#f2 (pdl129 only), and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the cmos standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device en- ergy consumption. the device automatically enables this mode when addresses remain stable for t acc + 150 ns. the automatic sleep mode is independent of the ce#f1/ce#f2 (pdl129 only), we#, and oe# con- trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always avail- able to the system. note that during automatic sleep mode, oe# must be at v ih before the device reduces current to the stated sleep mode specification. i cc5 in the dc characteristics table represents the automatic sleep mode current specification.
december 16, 2003 am49pdl127bh/am49pdl129bh 17 advance information reset#: hardware reset pin the reset# pin provides a hardware method of re- setting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory. if reset# is asserted during a program or erase op- eration, the ry/by# pin remains a ?0? (busy) until the internal reset operation is complete, which requires a time of t ready (during embedded algorithms). the sys- tem can thus monitor ry/by# to determine whether the reset operation is complete. if reset# is asserted when a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo- rithms). the system can read data t rh after the re- set# pin returns to v ih . refer to the psram ac characteristics tables for re- set# parameters and to figure 16 for the timing dia- gram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins (except for ry/by#) are placed in the highest impedance state
18 am49pdl127bh/am49pdl129bh december 16, 2003 advance information table 5. am29pdl127h sector architecture bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank a sa0 00000000000 4 000000h?000fffh sa1 00000000001 4 001000h?001fffh sa2 00000000010 4 002000h?002fffh sa3 00000000011 4 003000h?003fffh sa4 00000000100 4 004000h?004fffh sa5 00000000101 4 005000h?005fffh sa6 00000000110 4 006000h?006fffh sa7 00000000111 4 007000h?007fffh sa8 00000001xxx 32 008000h?00ffffh sa9 00000010xxx 32 010000h?017fffh sa10 00000011xxx 32 018000h?01ffffh sa11 00000100xxx 32 020000h?027fffh sa12 00000101xxx 32 028000h?02ffffh sa13 00000110xxx 32 030000h?037fffh sa14 00000111xxx 32 038000h?03ffffh sa15 00001000xxx 32 040000h?047fffh sa16 00001001xxx 32 048000h?04ffffh sa17 00001010xxx 32 050000h?057fffh sa18 00001011xxx 32 058000h?05ffffh sa19 00001100xxx 32 060000h?067fffh sa20 00001101xxx 32 068000h?06ffffh sa21 00001110xxx 32 070000h?077fffh sa22 00001111xxx 32 078000h?07ffffh sa23 00010000xxx 32 080000h?087fffh sa24 00010001xxx 32 088000h?08ffffh sa25 00010010xxx 32 090000h?097fffh sa26 00010011xxx 32 098000h?09ffffh sa27 00010100xxx 32 0a0000h?0a7fffh sa28 00010101xxx 32 0a8000h?0affffh sa29 00010110xxx 32 0b0000h?0b7fffh sa30 00010111xxx 32 0b8000h?0bffffh sa31 00011000xxx 32 0c0000h?0c7fffh sa32 00011001xxx 32 0c8000h?0cffffh sa33 00011010xxx 32 0d0000h?0d7fffh sa34 00011011xxx 32 0d8000h?0dffffh sa35 00011100xxx 32 0e0000h?0e7fffh sa36 00011101xxx 32 0e8000h?0effffh sa37 00011110xxx 32 0f0000h?0f7fffh sa38 00011111xxx 32 0f8000h?0fffffh bank sector sector address (a22-a12) sector size (kwords) address range (x16)
december 16, 2003 am49pdl127bh/am49pdl129bh 19 advance information bank b sa39 00100000xxx 32 100000h?107fffh sa40 00100001xxx 32 108000h?10ffffh sa41 00100010xxx 32 110000h?117fffh sa42 00100011xxx 32 118000h?11ffffh sa43 00100100xxx 32 120000h?127fffh sa44 00100101xxx 32 128000h?12ffffh sa45 00100110xxx 32 130000h?137fffh sa46 00100111xxx 32 138000h?13ffffh sa47 00101000xxx 32 140000h?147fffh sa48 00101001xxx 32 148000h?14ffffh sa49 00101010xxx 32 150000h?157fffh sa50 00101011xxx 32 158000h?15ffffh sa51 00101100xxx 32 160000h?167fffh sa52 00101101xxx 32 168000h?16ffffh sa53 00101110xxx 32 170000h?177fffh sa54 00101111xxx 32 178000h?17ffffh sa55 00110000xxx 32 180000h?187fffh sa56 00110001xxx 32 188000h?18ffffh sa57 00110010xxx 32 190000h?197fffh sa58 00110011xxx 32 198000h?19ffffh sa59 00110100xxx 32 1a0000h?1a7fffh sa60 00110101xxx 32 1a8000h?1affffh sa61 00110110xxx 32 1b0000h?1b7fffh sa62 00110111xxx 32 1b8000h?1bffffh sa63 00111000xxx 32 1c0000h?1c7fffh sa64 00111001xxx 32 1c8000h?1cffffh sa65 00111010xxx 32 1d0000h?1d7fffh sa66 00111011xxx 32 1d8000h?1dffffh sa67 00111100xxx 32 1e0000h?1e7fffh sa68 00111101xxx 32 1e8000h?1effffh sa69 00111110xxx 32 1f0000h?1f7fffh sa70 00111111xxx 32 1f8000h?1fffffh sa71 01000000xxx 32 200000h?207fffh sa72 01000001xxx 32 208000h?20ffffh sa73 01000010xxx 32 210000h?217fffh sa74 01000011xxx 32 218000h?21ffffh sa75 01000100xxx 32 220000h?227fffh sa76 01000101xxx 32 228000h?22ffffh sa77 01000110xxx 32 230000h?237fffh sa78 01000111xxx 32 238000h?23ffffh bank sector sector address (a22-a12) sector size (kwords) address range (x16) table 5. am29pdl127h sector architecture (continued)
20 am49pdl127bh/am49pdl129bh december 16, 2003 advance information bank b sa79 01001000xxx 32 240000h?247fffh sa80 01001001xxx 32 248000h?24ffffh sa81 01001010xxx 32 250000h?257fffh sa82 01001011xxx 32 258000h?25ffffh sa83 01001100xxx 32 260000h?267fffh sa84 01001101xxx 32 268000h?26ffffh sa85 01001110xxx 32 270000h?277fffh sa86 01001111xxx 32 278000h?27ffffh sa87 01010000xxx 32 280000h?287fffh sa88 01010001xxx 32 288000h?28ffffh sa89 01010010xxx 32 290000h?297fffh sa90 01010011xxx 32 298000h?29ffffh sa91 01010100xxx 32 2a0000h?2a7fffh sa92 01010101xxx 32 2a8000h?2affffh sa93 01010110xxx 32 2b0000h?2b7fffh sa94 01010111xxx 32 2b8000h?2bffffh sa95 01011000xxx 32 2c0000h?2c7fffh sa96 01011001xxx 32 2c8000h?2cffffh sa97 01011010xxx 32 2d0000h?2d7fffh sa98 01011011xxx 32 2d8000h?2dffffh sa99 01011100xxx 32 2e0000h?2e7fffh sa100 01011101xxx 32 2e8000h?2effffh sa101 01011110xxx 32 2f0000h?2f7fffh sa102 01011111xxx 32 2f8000h?2fffffh sa103 01100000xxx 32 300000h?307fffh sa104 01100001xxx 32 308000h?30ffffh sa105 01100010xxx 32 310000h?317fffh sa106 01100011xxx 32 318000h?31ffffh sa107 01100100xxx 32 320000h?327fffh sa108 01100101xxx 32 328000h?32ffffh sa109 01100110xxx 32 330000h?337fffh sa110 01100111xxx 32 338000h?33ffffh sa111 01101000xxx 32 340000h?347fffh sa112 01101001xxx 32 348000h?34ffffh sa113 01101010xxx 32 350000h?357fffh sa114 01101011xxx 32 358000h?35ffffh sa115 01101100xxx 32 360000h?367fffh sa116 01101101xxx 32 368000h?36ffffh sa117 01101110xxx 32 370000h?377fffh sa118 01101111xxx 32 378000h?37ffffh bank sector sector address (a22-a12) sector size (kwords) address range (x16) table 5. am29pdl127h sector architecture (continued)
december 16, 2003 am49pdl127bh/am49pdl129bh 21 advance information bank b sa119 01110000xxx 32 380000h?387fffh sa120 01110001xxx 32 388000h?38ffffh sa121 01110010xxx 32 390000h?397fffh sa122 01110011xxx 32 398000h?39ffffh sa123 01110100xxx 32 3a0000h?3a7fffh sa124 01110101xxx 32 3a8000h?3affffh sa125 01110110xxx 32 3b0000h?3b7fffh sa126 01110111xxx 32 3b8000h?3bffffh sa127 01111000xxx 32 3c0000h?3c7fffh sa128 01111001xxx 32 3c8000h?3cffffh sa129 01111010xxx 32 3d0000h?3d7fffh sa130 01111011xxx 32 3d8000h?3dffffh sa131 01111100xxx 32 3e0000h?3e7fffh sa132 01111101xxx 32 3e8000h?3effffh sa133 01111110xxx 32 3f0000h?3f7fffh sa134 01111111xxx 32 3f8000h?3fffffh bank c sa135 10000000xxx 32 400000h?407fffh sa136 10000001xxx 32 408000h?40ffffh sa137 10000010xxx 32 410000h?417fffh sa138 10000011xxx 32 418000h?41ffffh sa139 10000100xxx 32 420000h?427fffh sa140 10000101xxx 32 428000h?42ffffh sa141 10000110xxx 32 430000h?437fffh sa142 10000111xxx 32 438000h?43ffffh sa143 10001000xxx 32 440000h?447fffh sa144 10001001xxx 32 448000h?44ffffh sa145 10001010xxx 32 450000h?457fffh sa146 10001011xxx 32 458000h?45ffffh sa147 10001100xxx 32 460000h?467fffh sa148 10001101xxx 32 468000h?46ffffh sa149 10001110xxx 32 470000h?477fffh sa150 10001111xxx 32 478000h?47ffffh sa151 10010000xxx 32 480000h?487fffh sa152 10010001xxx 32 488000h?48ffffh sa153 10010010xxx 32 490000h?497fffh sa154 10010011xxx 32 498000h?49ffffh sa155 10010100xxx 32 4a0000h?4a7fffh sa156 10010101xxx 32 4a8000h?4affffh sa157 10010110xxx 32 4b0000h?4b7fffh sa158 10010111xxx 32 4b8000h?4bffffh bank sector sector address (a22-a12) sector size (kwords) address range (x16) table 5. am29pdl127h sector architecture (continued)
22 am49pdl127bh/am49pdl129bh december 16, 2003 advance information bank c sa159 10011000xxx 32 4c0000h?4c7fffh sa160 10011001xxx 32 4c8000h?4cffffh sa161 10011010xxx 32 4d0000h?4d7fffh sa162 10011011xxx 32 4d8000h?4dffffh sa163 10011100xxx 32 4e0000h?4e7fffh sa164 10011101xxx 32 4e8000h?4effffh sa165 10011110xxx 32 4f0000h?4f7fffh sa166 10011111xxx 32 4f8000h?4fffffh sa167 10100000xxx 32 500000h?507fffh sa168 10100001xxx 32 508000h?50ffffh sa169 10100010xxx 32 510000h?517fffh sa170 10100011xxx 32 518000h?51ffffh sa171 10100100xxx 32 520000h?527fffh sa172 10100101xxx 32 528000h?52ffffh sa173 10100110xxx 32 530000h?537fffh sa174 10100111xxx 32 538000h?53ffffh sa175 10101000xxx 32 540000h?547fffh sa176 10101001xxx 32 548000h?54ffffh sa177 10101010xxx 32 550000h?557fffh sa178 10101011xxx 32 558000h?15ffffh sa179 10101100xxx 32 560000h?567fffh sa180 10101101xxx 32 568000h?56ffffh sa181 10101110xxx 32 570000h?577fffh sa182 10101111xxx 32 578000h?57ffffh sa183 10110000xxx 32 580000h?587fffh sa184 10110001xxx 32 588000h?58ffffh sa185 10110010xxx 32 590000h?597fffh sa186 10110011xxx 32 598000h?59ffffh sa187 10110100xxx 32 5a0000h?5a7fffh sa188 10110101xxx 32 5a8000h?5affffh sa189 10110110xxx 32 5b0000h?5b7fffh sa190 10110111xxx 32 5b8000h?5bffffh sa191 10111000xxx 32 5c0000h?5c7fffh sa192 10111001xxx 32 5c8000h?5cffffh sa193 10111010xxx 32 5d0000h?5d7fffh sa194 10111011xxx 32 5d8000h?5dffffh sa195 10111100xxx 32 5e0000h?5e7fffh sa196 10111101xxx 32 5e8000h?5effffh sa197 10111110xxx 32 5f0000h?5f7fffh sa198 10111111xxx 32 5f8000h?5fffffh bank sector sector address (a22-a12) sector size (kwords) address range (x16) table 5. am29pdl127h sector architecture (continued)
december 16, 2003 am49pdl127bh/am49pdl129bh 23 advance information bank c sa199 11000000xxx 32 600000h?607fffh sa200 11000001xxx 32 608000h?60ffffh sa201 11000010xxx 32 610000h?617fffh sa202 11000011xxx 32 618000h?61ffffh sa203 11000100xxx 32 620000h?627fffh sa204 11000101xxx 32 628000h?62ffffh sa205 11000110xxx 32 630000h?637fffh sa206 11000111xxx 32 638000h?63ffffh sa207 11001000xxx 32 640000h?647fffh sa208 11001001xxx 32 648000h?64ffffh sa209 11001010xxx 32 650000h?657fffh sa210 11001011xxx 32 658000h?65ffffh sa211 11001100xxx 32 660000h?667fffh sa212 11001101xxx 32 668000h?66ffffh sa213 11001110xxx 32 670000h?677fffh sa214 11001111xxx 32 678000h?67ffffh sa215 11010000xxx 32 680000h?687fffh sa216 11010001xxx 32 688000h?68ffffh sa217 11010010xxx 32 690000h?697fffh sa218 11010011xxx 32 698000h?69ffffh sa219 11010100xxx 32 6a0000h?6a7fffh sa220 11010101xxx 32 6a8000h?6affffh sa221 11010110xxx 32 6b0000h?6b7fffh sa222 11010111xxx 32 6b8000h?6bffffh sa223 11011000xxx 32 6c0000h?6c7fffh sa224 11011001xxx 32 6c8000h?6cffffh sa225 11011010xxx 32 6d0000h?6d7fffh sa226 11011011xxx 32 6d8000h?6dffffh sa227 11011100xxx 32 6e0000h?6e7fffh sa228 11011101xxx 32 6e8000h?6effffh sa229 11011110xxx 32 6f0000h?6f7fffh sa230 11011111xxx 32 6f8000h?6fffffh table 5. am29pdl127h sector architecture (continued)
24 am49pdl127bh/am49pdl129bh december 16, 2003 advance information bank sector sector address (a22-a12) sector size (kwords) address range (x16) bank d sa231 11100000xxx 32 700000h?707fffh sa232 11100001xxx 32 708000h?70ffffh sa233 11100010xxx 32 710000h?717fffh sa234 11100011xxx 32 718000h?71ffffh sa235 11100100xxx 32 720000h?727fffh sa236 11100101xxx 32 728000h?72ffffh sa237 11100110xxx 32 730000h?737fffh sa238 11100111xxx 32 738000h?73ffffh sa239 11101000xxx 32 740000h?747fffh sa240 11101001xxx 32 748000h?74ffffh sa241 11101010xxx 32 750000h?757fffh sa242 11101011xxx 32 758000h?75ffffh sa243 11101100xxx 32 760000h?767fffh sa244 11101101xxx 32 768000h?76ffffh sa245 11101110xxx 32 770000h?777fffh sa246 11101111xxx 32 778000h?77ffffh sa247 11110000xxx 32 780000h?787fffh sa248 11110001xxx 32 788000h?78ffffh sa249 11110010xxx 32 790000h?797fffh sa250 11110011xxx 32 798000h?79ffffh sa251 11110100xxx 32 7a0000h?7a7fffh sa252 11110101xxx 32 7a8000h?7affffh sa253 11110110xxx 32 7b0000h?7b7fffh sa254 11110111xxx 32 7b8000h?7bffffh sa255 11111000xxx 32 7c0000h?7c7fffh sa256 11111001xxx 32 7c8000h?7cffffh sa257 11111010xxx 32 7d0000h?7d7fffh sa258 11111011xxx 32 7d8000h?7dffffh sa259 11111100xxx 32 7e0000h?7e7fffh sa260 11111101xxx 32 7e8000h?7effffh sa261 11111110xxx 32 7f0000h?7f7fffh sa262 11111111000 4 7f8000h?7f8fffh sa263 11111111001 4 7f9000h?7f9fffh sa264 11111111010 4 7fa000h?7fafffh sa265 11111111011 4 7fb000h?7fbfffh sa266 11111111100 4 7fc000h?7fcfffh sa267 11111111101 4 7fd000h?7fdfffh sa268 11111111110 4 7fe000h?7fefffh sa269 11111111111 4 7ff000h?7fffffh table 5. am29pdl127h sector architecture (continued)
december 16, 2003 am49pdl127bh/am49pdl129bh 25 advance information table 6. am29pdl129h sector architecture bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) bank a sa0 0 1 0000000000 4 000000h?000fffh sa1 0 1 0000000001 4 001000h?001fffh sa2 0 1 0000000010 4 002000h?002fffh sa3 0 1 0000000011 4 003000h?003fffh sa4 0 1 0000000100 4 004000h?004fffh sa5 0 1 0000000001 4 005000h?005fffh sa6 0 1 0000000010 4 006000h?006fffh sa7 0 1 0000000011 4 007000h?007fffh sa8 0 1 0000001xxx 32 008000h?00ffffh sa9 0 1 0000010xxx 32 010000h?017fffh sa10 0 1 0000011xxx 32 018000h?01ffffh sa11 0 1 0000100xxx 32 020000h?027fffh sa12 0 1 0000101xxx 32 028000h?02ffffh sa13 0 1 0000110xxx 32 030000h?037fffh sa14 0 1 0000111xxx 32 038000h?03ffffh sa15 0 1 0001000xxx 32 040000h?047fffh sa16 0 1 0001001xxx 32 048000h?04ffffh sa17 0 1 0001010xxx 32 050000h?057fffh sa18 0 1 0001011xxx 32 058000h?05ffffh sa19 0 1 0001100xxx 32 060000h?067fffh sa20 0 1 0001101xxx 32 068000h?06ffffh sa21 0 1 0001110xxx 32 070000h?077fffh sa22 0 1 0001111xxx 32 078000h?07ffffh sa23 0 1 0010000xxx 32 080000h?087fffh sa24 0 1 0010001xxx 32 088000h?08ffffh sa25 0 1 0010010xxx 32 090000h?097fffh sa26 0 1 0010011xxx 32 098000h?09ffffh sa27 0 1 0010100xxx 32 0a0000h?0a7fffh sa28 0 1 0010101xxx 32 0a8000h?0affffh sa29 0 1 0010110xxx 32 0b0000h?0b7fffh sa30 0 1 0010111xxx 32 0b8000h?0bffffh sa31 0 1 0011000xxx 32 0c0000h?0c7fffh sa32 0 1 0011001xxx 32 0c8000h?0cffffh sa33 0 1 0011010xxx 32 0d0000h?0d7fffh sa34 0 1 0011011xxx 32 0d8000h?0dffffh sa35 0 1 0011100xxx 32 0e0000h?0e7fffh sa36 0 1 0011101xxx 32 0e8000h?0effffh sa37 0 1 0011110xxx 32 0f0000h?0f7fffh sa38 0 1 0011111xxx 32 0f8000h?0fffffh bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16)
26 am49pdl127bh/am49pdl129bh december 16, 2003 advance information bank b sa39 0 1 0100000xxx 32 100000h?107fffh sa40 0 1 0100001xxx 32 108000h?10ffffh sa41 0 1 0100010xxx 32 110000h?117fffh sa42 0 1 0100011xxx 32 118000h?11ffffh sa43 0 1 0100100xxx 32 120000h?127fffh sa44 0 1 0100101xxx 32 128000h?12ffffh sa45 0 1 0100110xxx 32 130000h?137fffh sa46 0 1 0100111xxx 32 138000h?13ffffh sa47 0 1 0101000xxx 32 140000h?147fffh sa48 0 1 0101001xxx 32 148000h?14ffffh sa49 0 1 0101010xxx 32 150000h?157fffh sa50 0 1 0101011xxx 32 158000h?15ffffh sa51 0 1 0101100xxx 32 160000h?167fffh sa52 0 1 0101101xxx 32 168000h?16ffffh sa53 0 1 0101110xxx 32 170000h?177fffh sa54 0 1 0101111xxx 32 178000h?17ffffh sa55 0 1 0110000xxx 32 180000h?187fffh sa56 0 1 0110001xxx 32 188000h?18ffffh sa57 0 1 0110010xxx 32 190000h?197fffh sa58 0 1 0110011xxx 32 198000h?19ffffh sa59 0 1 0110100xxx 32 1a0000h?1a7fffh sa60 0 1 0110101xxx 32 1a8000h?1affffh sa61 0 1 0110110xxx 32 1b0000h?1b7fffh sa62 0 1 0110111xxx 32 1b8000h?1bffffh sa63 0 1 0111000xxx 32 1c0000h?1c7fffh sa64 0 1 0111001xxx 32 1c8000h?1cffffh sa65 0 1 0111010xxx 32 1d0000h?1d7fffh sa66 0 1 0111011xxx 32 1d8000h?1dffffh sa67 0 1 0111100xxx 32 1e0000h?1e7fffh sa68 0 1 0111101xxx 32 1e8000h?1effffh sa69 0 1 0111110xxx 32 1f0000h?1f7fffh sa70 0 1 0111111xxx 32 1f8000h?1fffffh sa71 0 1 1000000xxx 32 200000h?207fffh sa72 0 1 1000001xxx 32 208000h?20ffffh sa73 0 1 1000010xxx 32 210000h?217fffh sa74 0 1 1000011xxx 32 218000h?21ffffh sa75 0 1 1000100xxx 32 220000h?227fffh sa76 0 1 1000101xxx 32 228000h?22ffffh sa77 0 1 1000110xxx 32 230000h?237fffh sa78 0 1 1000111xxx 32 238000h?23ffffh bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) table 6. am29pdl129h sector architecture (continued)
december 16, 2003 am49pdl127bh/am49pdl129bh 27 advance information bank b sa79 0 1 1001000xxx 32 240000h?247fffh sa80 0 1 1001001xxx 32 248000h?24ffffh sa81 0 1 1001010xxx 32 250000h?257fffh sa82 0 1 1001011xxx 32 258000h?25ffffh sa83 0 1 1001100xxx 32 260000h?267fffh sa84 0 1 1001101xxx 32 268000h?26ffffh sa85 0 1 1001110xxx 32 270000h?277fffh sa86 0 1 1001111xxx 32 278000h?27ffffh sa87 0 1 1010000xxx 32 280000h?287fffh sa88 0 1 1010001xxx 32 288000h?28ffffh sa89 0 1 1010010xxx 32 290000h?297fffh sa90 0 1 1010011xxx 32 298000h?29ffffh sa91 0 1 1010100xxx 32 2a0000h?2a7fffh sa92 0 1 1010101xxx 32 2a8000h?2affffh sa93 0 1 1010110xxx 32 2b0000h?2b7fffh sa94 0 1 1010111xxx 32 2b8000h?2bffffh sa95 0 1 1011000xxx 32 2c0000h?2c7fffh sa96 0 1 1011001xxx 32 2c8000h?2cffffh sa97 0 1 1011010xxx 32 2d0000h?2d7fffh sa98 0 1 1011011xxx 32 2d8000h?2dffffh sa99 0 1 1011100xxx 32 2e0000h?2e7fffh sa100 0 1 1011101xxx 32 2e8000h?2effffh sa101 0 1 1011110xxx 32 2f0000h?2f7fffh sa102 0 1 1011111xxx 32 2f8000h?2fffffh sa103 0 1 1100000xxx 32 300000h?307fffh sa104 0 1 1100001xxx 32 308000h?30ffffh sa105 0 1 1100010xxx 32 310000h?317fffh sa106 0 1 1100011xxx 32 318000h?31ffffh sa107 0 1 1100100xxx 32 320000h?327fffh sa108 0 1 1100101xxx 32 328000h?32ffffh sa109 0 1 1100110xxx 32 330000h?337fffh sa110 0 1 1100111xxx 32 338000h?33ffffh sa111 0 1 1101000xxx 32 340000h?347fffh sa112 0 1 1101001xxx 32 348000h?34ffffh sa113 0 1 1101010xxx 32 350000h?357fffh sa114 0 1 1101011xxx 32 358000h?35ffffh sa115 0 1 1101100xxx 32 360000h?367fffh sa116 0 1 1101101xxx 32 368000h?36ffffh sa117 0 1 1101110xxx 32 370000h?377fffh sa118 0 1 1101111xxx 32 378000h?37ffffh bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) table 6. am29pdl129h sector architecture (continued)
28 am49pdl127bh/am49pdl129bh december 16, 2003 advance information bank b sa119 0 1 1110000xxx 32 380000h?387fffh sa120 0 1 1110001xxx 32 388000h?38ffffh sa121 0 1 1110010xxx 32 390000h?397fffh sa122 0 1 1110011xxx 32 398000h?39ffffh sa123 0 1 1110100xxx 32 3a0000h?3a7fffh sa124 0 1 1110101xxx 32 3a8000h?3affffh sa125 0 1 1110110xxx 32 3b0000h?3b7fffh sa126 0 1 1110111xxx 32 3b8000h?3bffffh sa127 0 1 1111000xxx 32 3c0000h?3c7fffh sa128 0 1 1111001xxx 32 3c8000h?3cffffh sa129 0 1 1111010xxx 32 3d0000h?3d7fffh sa130 0 1 1111011xxx 32 3d8000h?3dffffh sa131 0 1 1111100xxx 32 3e0000h?3e7fffh sa132 0 1 1111101xxx 32 3e8000h?3effffh sa133 0 1 1111110xxx 32 3f0000h?3f7fffh sa134 0 1 1111111xxx 32 3f8000h?3fffffh table 6. am29pdl129h sector architecture (continued)
december 16, 2003 am49pdl127bh/am49pdl129bh 29 advance information bank c sa135 1 0 0000000xxx 32 000000h?007fffh sa136 1 0 0000001xxx 32 008000h?00ffffh sa137 1 0 0000010xxx 32 010000h?017fffh sa138 1 0 0000011xxx 32 018000h?01ffffh sa139 1 0 0000100xxx 32 020000h?027fffh sa140 1 0 0000101xxx 32 028000h?02ffffh sa141 1 0 0000110xxx 32 030000h?037fffh sa142 1 0 0000111xxx 32 038000h?03ffffh sa143 1 0 0001000xxx 32 040000h?047fffh sa144 1 0 0001001xxx 32 048000h?04ffffh sa145 1 0 0001010xxx 32 050000h?057fffh sa146 1 0 0001011xxx 32 058000h?05ffffh sa147 1 0 0001100xxx 32 060000h?067fffh sa148 1 0 0001101xxx 32 068000h?06ffffh sa149 1 0 0001110xxx 32 070000h?077fffh sa150 1 0 0001111xxx 32 078000h?07ffffh sa151 1 0 0010000xxx 32 080000h?087fffh sa152 1 0 0010001xxx 32 088000h?08ffffh sa153 1 0 0010010xxx 32 090000h?097fffh sa154 1 0 0010011xxx 32 098000h?09ffffh sa155 1 0 0010100xxx 32 0a0000h?0a7fffh sa156 1 0 0010101xxx 32 0a8000h?0affffh sa157 1 0 0010110xxx 32 0b0000h?0b7fffh sa158 1 0 0010111xxx 32 0b8000h?0bffffh bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) table 6. am29pdl129h sector architecture (continued)
30 am49pdl127bh/am49pdl129bh december 16, 2003 advance information bank c (continued) sa159 1 0 0011000xxx 32 0c0000h?0c7fffh sa160 1 0 0011001xxx 32 0c8000h?0cffffh sa161 1 0 0011010xxx 32 0d0000h?0d7fffh sa162 1 0 0011011xxx 32 0d8000h?0dffffh sa163 1 0 0011100xxx 32 0e0000h?0e7fffh sa164 1 0 0011101xxx 32 0e8000h?0effffh sa165 1 0 0011110xxx 32 0f0000h?0f7fffh sa166 1 0 0011111xxx 32 0f8000h?0fffffh sa167 1 0 0100000xxx 32 100000h?107fffh sa168 1 0 0100001xxx 32 108000h?10ffffh sa169 1 0 0100010xxx 32 110000h?117fffh sa170 1 0 0100011xxx 32 118000h?11ffffh sa171 1 0 0100100xxx 32 120000h?127fffh sa172 1 0 0100101xxx 32 128000h?12ffffh sa173 1 0 0100110xxx 32 130000h?137fffh sa174 1 0 0100111xxx 32 138000h?13ffffh sa175 1 0 0101000xxx 32 140000h?147fffh sa176 1 0 0101001xxx 32 148000h?14ffffh sa177 1 0 0101010xxx 32 150000h?157fffh sa178 1 0 0101011xxx 32 158000h?15ffffh sa179 1 0 0101100xxx 32 160000h?167fffh sa180 1 0 0101101xxx 32 168000h?16ffffh sa181 1 0 0101110xxx 32 170000h?177fffh sa182 1 0 0101111xxx 32 178000h?17ffffh sa183 1 0 0110000xxx 32 180000h?187fffh sa184 1 0 0110001xxx 32 188000h?18ffffh sa185 1 0 0110010xxx 32 190000h?197fffh sa186 1 0 0110011xxx 32 198000h?19ffffh sa187 1 0 0110100xxx 32 1a0000h?1a7fffh sa188 1 0 0110101xxx 32 1a8000h?1affffh sa189 1 0 0110110xxx 32 1b0000h?1b7fffh sa190 1 0 0110111xxx 32 1b8000h?1bffffh sa191 1 0 0111000xxx 32 1c0000h?1c7fffh sa192 1 0 0111001xxx 32 1c8000h?1cffffh sa193 1 0 0111010xxx 32 1d0000h?1d7fffh sa194 1 0 0111011xxx 32 1d8000h?1dffffh sa195 1 0 0111100xxx 32 1e0000h?1e7fffh sa196 1 0 0111101xxx 32 1e8000h?1effffh sa197 1 0 0111110xxx 32 1f0000h?1f7fffh sa198 1 0 0111111xxx 32 1f8000h?1fffffh bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) table 6. am29pdl129h sector architecture (continued)
december 16, 2003 am49pdl127bh/am49pdl129bh 31 advance information bank c (continued) sa199 1 0 1000000xxx 32 200000h?207fffh sa200 1 0 1000001xxx 32 208000h?20ffffh sa201 1 0 1000010xxx 32 210000h?217fffh sa202 1 0 1000011xxx 32 218000h?21ffffh sa203 1 0 1000100xxx 32 220000h?227fffh sa204 1 0 1000101xxx 32 228000h?22ffffh sa205 1 0 1000110xxx 32 230000h?237fffh sa206 1 0 1000111xxx 32 238000h?23ffffh sa207 1 0 1001000xxx 32 240000h?247fffh sa208 1 0 1001001xxx 32 248000h?24ffffh sa209 1 0 1001010xxx 32 250000h?257fffh sa210 1 0 1001011xxx 32 258000h?25ffffh sa211 1 0 1001100xxx 32 260000h?267fffh sa212 1 0 1001101xxx 32 268000h?26ffffh sa213 1 0 1001110xxx 32 270000h?277fffh sa214 1 0 1001111xxx 32 278000h?27ffffh sa215 1 0 1010000xxx 32 280000h?287fffh sa216 1 0 1010001xxx 32 288000h?28ffffh sa217 1 0 1010010xxx 32 290000h?297fffh sa218 1 0 1010011xxx 32 298000h?29ffffh sa219 1 0 1010100xxx 32 2a0000h?2a7fffh sa220 1 0 1010101xxx 32 2a8000h?2affffh sa221 1 0 1010110xxx 32 2b0000h?2b7fffh sa222 1 0 1010111xxx 32 2b8000h?2bffffh sa223 1 0 1011000xxx 32 2c0000h?2c7fffh sa224 1 0 1011001xxx 32 2c8000h?2cffffh sa225 1 0 1011010xxx 32 2d0000h?2d7fffh sa226 1 0 1011011xxx 32 2d8000h?2dffffh sa227 1 0 1011100xxx 32 2e0000h?2e7fffh sa228 1 0 1011101xxx 32 2e8000h?2effffh sa229 1 0 1011110xxx 32 2f0000h?2f7fffh sa230 1 0 1011111xxx 32 2f8000h?2fffffh bank sector ce#f1 ce#f2 sector address (a21-a12) sector size (kwords) address range (x16) table 6. am29pdl129h sector architecture (continued)
32 am49pdl127bh/am49pdl129bh december 16, 2003 advance information table 7. secsi tm sector addresses bank d sa231 1 0 1100000xxx 32 300000h?307fffh sa232 1 0 1100001xxx 32 308000h?30ffffh sa233 1 0 1100010xxx 32 310000h?317fffh sa234 1 0 1100011xxx 32 318000h?31ffffh sa235 1 0 1100100xxx 32 320000h?327fffh sa236 1 0 1100101xxx 32 328000h?32ffffh sa237 1 0 1100110xxx 32 330000h?337fffh sa238 1 0 1100111xxx 32 338000h?33ffffh sa239 1 0 1101000xxx 32 340000h?347fffh sa240 1 0 1101001xxx 32 348000h?34ffffh sa241 1 0 1101010xxx 32 350000h?357fffh sa242 1 0 1101011xxx 32 358000h?35ffffh sa243 1 0 1101100xxx 32 360000h?367fffh sa244 1 0 1101101xxx 32 368000h?36ffffh sa245 1 0 1101110xxx 32 370000h?377fffh sa246 1 0 1101111xxx 32 378000h?37ffffh sa247 1 0 1110000xxx 32 380000h?387fffh sa248 1 0 1110001xxx 32 388000h?38ffffh sa249 1 0 1110010xxx 32 390000h?397fffh sa250 1 0 1110011xxx 32 398000h?39ffffh sa251 1 0 1110100xxx 32 3a0000h?3a7fffh sa252 1 0 1110101xxx 32 3a8000h?3affffh sa253 1 0 1110110xxx 32 3b0000h?3b7fffh sa254 1 0 1110111xxx 32 3b8000h?3bffffh sa255 1 0 1111000xxx 32 3c0000h?3c7fffh sa256 1 0 1111001xxx 32 3c8000h?3cffffh sa257 1 0 1111010xxx 32 3d0000h?3d7fffh sa258 1 0 1111011xxx 32 3d8000h?3dffffh sa259 1 0 1111100xxx 32 3e0000h?3e7fffh sa260 1 0 1111101xxx 32 3e8000h?3effffh sa261 1 0 1111110xxx 32 3f0000h?3f7fffh sa262 1 0 1111111000 32 3f8000h?3f8fffh sa263 1 0 1111111001 4 3f9000h?3f9fffh sa264 1 0 1111111010 4 3fa000h?3fafffh sa265 1 0 1111111011 4 3fb000h?3fbfffh sa266 1 0 1111111100 4 3fc000h?3fcfffh sa267 1 0 1111111101 4 3fd000h?3fdfffh sa268 1 0 1111111110 4 3fe000h?3fefffh sa269 1 0 1111111111 4 3ff000h?3fffffh table 6. am29pdl129h sector architecture (continued) secsi sector area sector size address range factory-locked area 64 words 000000h-00003fh customer-lockable area 64 words 000040h-00007fh secsi sector area sector size address range
december 16, 2003 am49pdl127bh/am49pdl129bh 33 advance information table 8. am29pdl127h boot sector/sector block addresses for protection/unprotection sector a22-a12 sector/ sector block size sa0 00000000000 4 kwords sa1 00000000001 4 kwords sa2 00000000010 4 kwords sa3 00000000011 4 kwords sa4 00000000100 4 kwords sa5 00000000101 4 kwords sa6 00000000110 4 kwords sa7 00000000111 4 kwords sa8?sa10 00000001xxx 00000010xxx 00000011xxx 96 (3x32) kwords sa11?sa14 000001xxxxx 128 (4x32) kwords sa15?sa18 000010xxxxx 128 (4x32) kwords sa19?sa22 000011xxxxx 128 (4x32) kwords sa23?sa26 000100xxxxx 128 (4x32) kwords sa27?sa30 000101xxxxx 128 (4x32) kwords sa31?sa34 000110xxxxx 128 (4x32) kwords sa35?sa38 000111xxxxx 128 (4x32) kwords sa39?sa42 001000xxxxx 128 (4x32) kwords sa43?sa46 001001xxxxx 128 (4x32) kwords sa47?sa50 001010xxxxx 128 (4x32) kwords sa51?sa54 001011xxxxx 128 (4x32) kwords sa55?sa58 001100xxxxx 128 (4x32) kwords sa59?sa62 001101xxxxx 128 (4x32) kwords sa63?sa66 001110xxxxx 128 (4x32) kwords sa67?sa70 001111xxxxx 128 (4x32) kwords sa71?sa74 010000xxxxx 128 (4x32) kwords sa75?sa78 010001xxxxx 128 (4x32) kwords sa79?sa82 010010xxxxx 128 (4x32) kwords sa83?sa86 010011xxxxx 128 (4x32) kwords sa87?sa90 010100xxxxx 128 (4x32) kwords sa91?sa94 010101xxxxx 128 (4x32) kwords sa95?sa98 010110xxxxx 128 (4x32) kwords sa99?sa102 010111xxxxx 128 (4x32) kwords sa103?sa106 011000xxxxx 128 (4x32) kwords sa107?sa110 011001xxxxx 128 (4x32) kwords sa111?sa114 011010xxxxx 128 (4x32) kwords sa115?sa118 011011xxxxx 128 (4x32) kwords sa119?sa122 011100xxxxx 128 (4x32) kwords sa123?sa126 011101xxxxx 128 (4x32) kwords sa127?sa130 011110xxxxx 128 (4x32) kwords sector a22-a12 sector/ sector block size sa131?sa134 011111xxxxx 128 (4x32) kwords sa135?sa138 100000xxxxx 128 (4x32) kwords sa139?sa142 100001xxxxx 128 (4x32) kwords sa143?sa146 100010xxxxx 128 (4x32) kwords sa147?sa150 100011xxxxx 128 (4x32) kwords sa151?sa154 100100xxxxx 128 (4x32) kwords sa155?sa158 100101xxxxx 128 (4x32) kwords sa159?sa162 100110xxxxx 128 (4x32) kwords sa163?sa166 100111xxxxx 128 (4x32) kwords sa167?sa170 101000xxxxx 128 (4x32) kwords sa171?sa174 101001xxxxx 128 (4x32) kwords sa175?sa178 101010xxxxx 128 (4x32) kwords sa179?sa182 101011xxxxx 128 (4x32) kwords sa183?sa186 101100xxxxx 128 (4x32) kwords sa187?sa190 101101xxxxx 128 (4x32) kwords sa191?sa194 101110xxxxx 128 (4x32) kwords sa195?sa198 101111xxxxx 128 (4x32) kwords sa199?sa202 110000xxxxx 128 (4x32) kwords sa203?sa206 110001xxxxx 128 (4x32) kwords sa207?sa210 110010xxxxx 128 (4x32) kwords sa211?sa214 110011xxxxx 128 (4x32) kwords sa215?sa218 110100xxxxx 128 (4x32) kwords sa219?sa222 110101xxxxx 128 (4x32) kwords sa223?sa226 110110xxxxx 128 (4x32) kwords sa227?sa230 110111xxxxx 128 (4x32) kwords sa231?sa234 111000xxxxx 128 (4x32) kwords sa235?sa238 111001xxxxx 128 (4x32) kwords sa239?sa242 111010xxxxx 128 (4x32) kwords sa243?sa246 111011xxxxx 128 (4x32) kwords sa247?sa250 111100xxxxx 128 (4x32) kwords sa251?sa254 111101xxxxx 128 (4x32) kwords sa255?sa258 111110xxxxx 128 (4x32) kwords sa259?sa261 11111100xxx 11111101xxx 11111110xxx 96 (3x32) kwords sa262 11111111000 4 kwords sa263 11111111001 4 kwords sa264 11111111010 4 kwords sa265 11111111011 4 kwords sa266 11111111100 4 kwords sa267 11111111101 4 kwords sa268 11111111110 4 kwords sa269 11111111111 4 kwords
34 am49pdl127bh/am49pdl129bh december 16, 2003 advance information table 9. am29pdl129h boot sector/sector block addresses for protection/unprotection sector ce#f1 ce#f2 a21?a12 sector/ sector block size sa0 0 1 0000000000 4 kwords sa1 0 1 0000000001 4 kwords sa2 0 1 0000000010 4 kwords sa3 0 1 0000000011 4 kwords sa4 0 1 0000000100 4 kwords sa5 0 1 0000000101 4 kwords sa6 0 1 0000000110 4 kwords sa7 0 1 0000000111 4 kwords sa8?sa10 0 1 0000001xxx 0000010xxx 0000011xxx 96 (3x32) kwords sa11?sa14 0 1 00001xxxxx 128 (4x32) kwords sa15?sa18 0 1 00010xxxxx 128 (4x32) kwords sa19?sa22 0 1 00011xxxxx 128 (4x32) kwords sa23?sa26 0 1 00100xxxxx 128 (4x32) kwords sa27?sa30 0 1 00101xxxxx 128 (4x32) kwords sa31?sa34 0 1 00110xxxxx 128 (4x32) kwords sa35?sa38 0 1 00111xxxxx 128 (4x32) kwords sa39?sa42 0 1 01000xxxxx 128 (4x32) kwords sa43?sa46 0 1 01001xxxxx 128 (4x32) kwords sa47?sa50 0 1 01010xxxxx 128 (4x32) kwords sa51?sa54 0 1 01011xxxxx 128 (4x32) kwords sa55?sa58 0 1 01100xxxxx 128 (4x32) kwords sa59?sa62 0 1 01101xxxxx 128 (4x32) kwords sa63?sa66 0 1 01110xxxxx 128 (4x32) kwords sa67?sa70 0 1 01111xxxxx 128 (4x32) kwords sa71?sa74 0 1 10000xxxxx 128 (4x32) kwords sa75?sa78 0 1 10001xxxxx 128 (4x32) kwords sa79?sa82 0 1 10010xxxxx 128 (4x32) kwords sa83?sa86 0 1 10011xxxxx 128 (4x32) kwords sa87?sa90 0 1 10100xxxxx 128 (4x32) kwords sa91?sa94 0 1 10101xxxxx 128 (4x32) kwords sa95?sa98 0 1 10110xxxxx 128 (4x32) kwords sa99?sa102 0 1 10111xxxxx 128 (4x32) kwords sa103?sa106 0 1 11000xxxxx 128 (4x32) kwords sa107?sa110 0 1 11001xxxxx 128 (4x32) kwords sa111?sa114 0 1 11010xxxxx 128 (4x32) kwords sa115?sa118 0 1 11011xxxxx 128 (4x32) kwords sa119?sa122 0 1 11100xxxxx 128 (4x32) kwords sa123?sa126 0 1 11101xxxxx 128 (4x32) kwords sector ce#f1 ce#f2 a21?a12 sector/ sector block size sa127?sa130 0 1 11110xxxxx 128 (4x32) kwords sa131?sa134 0 1 11111xxxxx 128 (4x32) kwords sa135?sa138 1 0 00000xxxxx 128 (4x32) kwords sa139?sa142 1 0 00001xxxxx 128 (4x32) kwords sa143?sa146 1 0 00010xxxxx 128 (4x32) kwords sa147?sa150 1 0 00011xxxxx 128 (4x32) kwords sa151?sa154 1 0 00100xxxxx 128 (4x32) kwords sa155?sa158 1 0 00101xxxxx 128 (4x32) kwords sa159?sa162 1 0 00110xxxxx 128 (4x32) kwords sa163?sa166 1 0 00111xxxxx 128 (4x32) kwords sa167?sa170 1 0 01000xxxxx 128 (4x32) kwords sa171?sa174 1 0 01001xxxxx 128 (4x32) kwords sa175?sa178 1 0 01010xxxxx 128 (4x32) kwords sa179?sa182 1 0 01011xxxxx 128 (4x32) kwords sa183?sa186 1 0 01100xxxxx 128 (4x32) kwords sa187?sa190 1 0 01101xxxxx 128 (4x32) kwords sa191?sa194 1 0 01110xxxxx 128 (4x32) kwords sa195?sa198 1 0 01111xxxxx 128 (4x32) kwords sa199?sa202 1 0 10000xxxxx 128 (4x32) kwords sa203?sa206 1 0 10001xxxxx 128 (4x32) kwords sa207?sa210 1 0 10010xxxxx 128 (4x32) kwords sa211?sa214 1 0 10011xxxxx 128 (4x32) kwords sa215?sa218 1 0 10100xxxxx 128 (4x32) kwords sa219?sa222 1 0 10101xxxxx 128 (4x32) kwords sa223?sa226 1 0 10110xxxxx 128 (4x32) kwords sa227?sa230 1 0 10111xxxxx 128 (4x32) kwords sa231?sa234 1 0 11000xxxxx 128 (4x32) kwords sa235?sa238 1 0 11001xxxxx 128 (4x32) kwords sa239?sa242 1 0 11010xxxxx 128 (4x32) kwords sa243?sa246 1 0 11011xxxxx 128 (4x32) kwords sa247?sa250 1 0 11100xxxxx 128 (4x32) kwords sa251?sa254 1 0 11101xxxxx 128 (4x32) kwords sa255?sa258 1 0 11110xxxxx 128 (4x32) kwords sa259?sa261 1 0 1111100xxx 1111101xxx 1111110xxx 96 (3x32) kwords sa262 1 0 1111111000 4 kwords sa263 1 0 1111111001 4 kwords sa264 1 0 1111111010 4 kwords sa265 1 0 1111111011 4 kwords sa266 1 0 1111111100 4 kwords sa267 1 0 1111111101 4 kwords sa268 1 0 1111111110 4 kwords sa269 1 0 1111111111 4 kwords
december 16, 2003 am49pdl127bh/am49pdl129bh 35 advance information sector protection the am29pdl127h/am29pdl129h features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: persistent sector protection a command sector protection method that replaces the old 12 v controlled protection method. password sector protection a highly sophisticated protection method that requires a password before changes to certain sectors or sec- tor groups are permitted. wp# hardware protection a write protect pin that can prevent program or erase operations in sectors 0, 1, 268, and 269. the wp# hardware protection feature is always available, re- gardless of which of the other two methods are cho- sen. selecting a sector protection mode the device defaults to the persistent sector protection mode. however, to prevents a program or virus from later setting the password mode locking bit, which would cause an unexpected shift from the default per- sistent sector protection mode into the password pro- tection mode, it is recommended that either of two one-time programmable non-volatile bits that perma- nently define which sector protection method be set before the device is first programmed . the persis- tent sector protection mode locking bit perma- nently sets the device to the persistent sector protection mode. the password mode locking bit permanently sets the device to the password sector protection mode. it is not possible to switch between the two protection modes once a locking bit has been set. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at the factory prior to shipping the device through amd?s expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is pro- tected or unprotected. see autoselect command se- quence for details. persistent sector protection the persistent sector protection method replaces the 12 v controlled protection method in previous amd flash devices. this new method provides three differ- ent sector protection states: persistently locked ?the sector is protected and cannot be changed. dynamically locked ?the sector is protected and can be changed by a simple command. unlocked ?the sector is unprotected and can be changed by a simple command. to achieve these states, three types of ?bits? are used: persistent protection bit (ppb) a single persistent (non-volatile) protection bit is as- signed to a maximum four sectors (see the sector ad- dress tables for specific sector protection groupings). all 4 kword boot-block sectors have individual sector persistent protection bits ( ppbs) for greater flexibility. each ppb is individually modifiable through the ppb write command . the device erases all ppbs in parallel. if any ppb re- quires erasure, the device must be instructed to pre- program all of the sector ppbs prior to ppb erasure. otherwise, a previously er ased sector ppbs can po- tentially be over-erased. the flash device does not have a built-in means of preventing sector ppbs over-erasure . persistent protection bit lock (ppb lock) the persistent protection bit lock (ppb lock) is a glo- bal volatile bit. when set to ?1?, the ppbs cannot be changed. when cleared (?0?), the ppbs are change- able. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command sequence to unlock the ppb lock. dynamic protection bit (dyb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dybs is ?0?. each dyb is individually modifiable through the dyb write command. when the parts are first shipped, the ppbs are cleared, the dybs are cleared, and ppb lock is de- faulted to power up in the cleared state ? meaning the ppbs are changeable. when the device is first powered on the dybs power up cleared (sectors not protected). the protection state for each sector is determined by the logical or of the ppb and the dyb related to that sector. for the sectors that have the ppbs cleared, the dybs control whether or not the sector is protected or unprotected. by issuing the dyb write command sequences, the dybs will be set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and un- protected conditions. this allows software to easily protect sectors against inadvertent changes yet does
36 am49pdl127bh/am49pdl129bh december 16, 2003 advance information not prevent the easy removal of protection when changes are needed. the dybs maybe set or cleared as often as needed. the ppbs allow for a more static, and difficult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. in- dividual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also limited to 100 erase cycles. the ppb lock bit adds an additional level of protec- tion. once all ppbs are programmed to the desired settings, the ppb lock may be set to ?1?. setting the ppb lock disables all program and erase commands to the non-volatile ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed; for example, to allow new system code to be downloaded. if no changes are needed then the boot code can set the ppb lock to disable any further changes to the ppbs during system opera- tion. the wp#/acc write protect pin adds a final level of hardware protection to sectors 0, 1, 268, and 269. when this pin is low it is not possible to change the contents of these sectors. these sectors generally hold system boot code. the wp#/acc pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. it is possible to have sectors that have been persis- tently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unpro- tected. if there is a need to protect some of them, a simple dyb write command sequence is all that is necessary. the dyb write command for the dynamic sectors switch the dybs to signify protected and un- protected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be dis- abled by either putting the device through a power-cy- cle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the de- vice operates normally again. the best protection is achieved by executing the ppb lock bit set command early in the boot code, and pro- tect the boot code by holding wp#/acc = v il . table 10. sector protection schemes table 10 contains all possible combinations of the dyb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the ppb lock. if the ppb is cleared, the sector can be dynami- cally locked or unlocked. the dyb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 s before the device returns to read mode without having modi- fied the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 s after which the device returns to read mode without having erased the protected sec- tor. the programming of the dyb, ppb, and ppb lock for a given sector can be verified by writing a dyb/ppb/ppb lock verify command to the device. persistent sector protection mode locking bit like the password mode locking bit, a persistent sec- tor protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit pre- vents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode. password protection mode the password sector protection mode method allows an even higher level of security than the persistent sector protection mode. there are two main differ- dyb ppb ppb lock sector state 000 unprotected?ppb and dyb are changeable 001 unprotected?ppb not changeable, dyb is changeable 010 protected?ppb and dyb are changeable 100 110 011 protected?ppb not changeable, dyb is changeable 101 111
december 16, 2003 am49pdl127bh/am49pdl129bh 37 advance information ences between the persistent sector protection and the password sector protection mode: when the device is first powered on, or comes out of a reset cycle, the ppb lock bit set to the locked state , rather than cleared to the unlocked state. the only means to clear the ppb lock bit is by writ- ing a unique 64-bit password to the device. the password sector protection method is otherwise identical to the persistent sector protection method. a 64-bit password is the only additional tool utilized in this method. once the password mode locking bit is set, the pass- word is permanently set with no means to read, pro- gram, or erase it. the password is used to clear the ppb lock bit. the password unlock command must be written to the flash, along with a password. the flash device internally compares the given password with the pre-programmed password. if they match, the ppb lock bit is cleared, and the ppbs can be altered. if they do not match, the flash device does nothing. there is a built-in 2 s delay for each ?password check.? this delay is intended to thwart any efforts to run a program that tries all possible combinations in order to crack the password. password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the pass- word. the password may be correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password re- gion, the customer may perform password verify oper- ations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: 1. permanently sets the device to operate using the password protection mode. it is not possible to re- verse this function. 2. disables all further commands to the password re- gion. all program, and read operations are ignored. both of these objectives are important, and if not care- fully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persistent sector protection lock- ing bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the pass- word program and verify commands (see ?password verify command?). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify com- mand from reading the contents of the password on the pins of the device. write protect (wp#) the write protect feature provides a hardware method of protecting sectors 0, 1, 268, and 269 without using v id . this function is provided by the wp# pin and over- rides the previously discussed high voltage sector protection method. if the system asserts v il on the wp#/acc pin, the de- vice disables program and erase functions in the two outermost 4 kword sectors on both ends of the flash array independent of whether it was previously pro- tected or unprotected. if the system asserts v ih on the wp#/acc pin, the de- vice reverts to whether sectors 0, 1, 268, and 269 were last set to be protected or unprotected. that is, sector protection or unprotection for these sectors de- pends on whether they were last protected or unpro- tected using the method described in high voltage sector protection. note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. persistent protection bit lock the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode lock- ing bit after power-up reset. if the password mode lock bit is also set after a hardware reset (reset# asserted) or a power-up reset, the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. suc- cessful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset#, taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit to a ?1? when the password mode lock bit is not set.
38 am49pdl127bh/am49pdl129bh december 16, 2003 advance information if the password mode locking bit is not set, including persistent protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set com- mand. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persis- tent protection mode. high voltage sector protection sector protection and unprotection may also be imple- mented using programming equipment. the proce- dure requires high voltage (v id ) to be placed on the reset# pin. refer to figure 1 for details on this pro- cedure. note that for sector unprotect, all unprotected sectors must first be protected prior to the first sector write cycle.
december 16, 2003 am49pdl127bh/am49pdl129bh 39 advance information figure 1. in-system sector protection/ sector unprotection algorithms sector protect: write 60h to sector address with a7-a0 = 00000010 set up sector address wait 100 s verify sector protect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a7-a0 = 01000010 set up first sector address wait 1.2 ms verify sector unprotect: write 40h to sector address with a7-a0 = 00000010 read from sector address with a7-a0 = 00000010 start plscnt = 1 reset# = v id wait 4 s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 remove v id from reset# write reset command sector protect complete remove v id from reset# write reset command sector unprotect complete
40 am49pdl127bh/am49pdl129bh december 16, 2003 advance information temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the re- set# pin, all the previously protected sectors are protected again. figure 2 shows the algorithm, and figure 24 shows the timing diagrams, for this feature. while ppb lock is set, the device cannot enter the temporary sector unprotection mode. figure 2. temporar y sector unprotect operation secsi? (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn) the 128-word secsi sector is divided into 64 factory-lockable words that can be programmed and locked by the customer. the secsi sector is located at addresses 000000h?00007fh in both persistent pro- tection mode and password protection mode. it uses indicator bits (dq6, dq7) to indicate the fac- tory-locked and customer-locked status of the part. the system accesses the secsi sector through a command sequence (see ?enter secsi? sector/exit secsi sector command sequence?). after the system has written the enter secsi sector command se- quence, it may read the secsi sector by using the ad- dresses normally occupied by the boot sectors. this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to send- ing commands to the normal address space. factory-locked area (64 words) the factory-locked area of the secsi sector (000000h?00003fh) is locked when the part is shipped, whether or not the area was programmed at the factory. the secsi sector factory-locked indicator bit (dq7) is permanently set to a ?1?. amd offers the expressflash service to program the factory-locked area with a random esn, a customer-defined code, or any combination of the two. because only amd can program and protect the factory-locked area, this method ensures the security of the esn once the product is shipped to the field. contact an amd repre- sentative for details on using amd?s expressflash ser- vice. note that the acc function and unlock bypass modes are not available when the secsi sector is en- abled. customer-lockable area (64 words) the customer-lockable area of the secsi sector (000040h?00007fh) is shipped unprotected, which al- lows the customer to program and optionally lock the area as appropriate for the application. the secsi sector customer-locked indicator bit (dq6) is shipped as ?0? and can be permanently locked to ?1? by issuing the secsi protection bit program command. the secsi sector can be read any number of times, but can be programmed and locked only once. note that the accelerated programming (acc) and unlock by- pass functions are not available when programming the secsi sector. the customer-lockable secsi sector area can be pro- tected using one of the following procedures: follow the secsi sector protection algorithm as shown in figure 3. this allows in-system protection of the secsi sector region without raising any de- vice pin to a high voltage. note that this method is only applicable to the secsi sector. notes: 1. all protected sectors unprotected (if wp#/acc = v il , sectors 0, 1, 268, 269 will remain protected). 2. all previously protected sectors are protected once again. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1)
december 16, 2003 am49pdl127bh/am49pdl129bh 41 advance information figure 3. pdl127h/129h secsi sector protection algorithm to verify the protect/unprotect status of the secsi sector, follow the algorithm shown in figure 4. once the secsi sector is locked and verified, the sys- tem must write the exit secsi sector region com- mand sequence to return to reading and writing the remainder of the array. the secsi sector lock must be used with caution since, once locked, there is no procedure available for unlocking the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. secsi sector protection bits the secsi sector protection bits prevent program- ming of the secsi sector memory area. once set, the start secsi tm sector entry write aah to address 555h write 55h to address 2aah write 88h to address 555h secsi sector protection entry write aah to address 555h write 55h to address 2aah write 60h to address 555h plscnt = 1 protect secsi sector: write 68h to sector address with a7?a0 = 00011010 time out 256 s read from sector address with a7?a0 = 00011010 data = 01h? yes yes secsi sector protection completed secsi sector exit write 555h/aah write 2aah/55h write sa0+555h/90h write xxxh/00h verify secsi sector: write 48h to sector address with a7?a0 = 00011010 increment plscnt plscnt = 25? device failed secsi sector entry secsi sector protection secsi sector exit no no
42 am49pdl127bh/am49pdl129bh december 16, 2003 advance information secsi sector memory area contents are non-modifi- able. figure 4. secsi sector protect verify hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes. in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, ce#f1, ce#f2 or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce#f1 =ce#f2 = v ih or we# = v ih . to initiate a write cycle, ce#f1/ce#f2 and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce#f1 = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automati- cally reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the sys- tem writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 11?14. to terminate reading cfi data, the system must write the reset command. the cfi query mode is not accessible when the device is exe- cuting an embedded program or embedded erase al- gorithm. the system can also write the cfi query command when the device is in the autoselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 11?14. the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specifi- cation and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alterna- tively, contact an amd representative for copies of these documents. write 60h to any address write 40h to secsi sector address with a6 = 0, a1 = 1, a0 = 0 start reset# = v ih or v id wait 1 s read from secsi sector address with a6 = 0, a1 = 1, a0 = 0 if data = 00h, secsi sector is unprotected. if data = 01h, secsi sector is protected. remove v ih or v id from reset# write reset command secsi sector protect verify complete
december 16, 2003 am49pdl127bh/am49pdl129bh 43 advance information table 11. cfi query identification string table 12. system interface string addresses data description 10h 11h 12h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 0002h 0000h primary oem command set 15h 16h 0040h 0000h address for primary extended table 17h 18h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 0000h 0000h address for alternate oem extended table (00h = none exists) addresses data description 1bh 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 0000h v pp min. voltage (00h = no v pp pin present) 1eh 0000h v pp max. voltage (00h = no v pp pin present) 1fh 0004h typical timeout per single byte/word write 2 n s 20h 0000h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 0009h typical timeout per individual block erase 2 n ms 22h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 0005h max. timeout for byte/word write 2 n times typical 24h 0000h max. timeout for buffer write 2 n times typical 25h 0004h max. timeout per individual block erase 2 n times typical 26h 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
44 am49pdl127bh/am49pdl129bh december 16, 2003 advance information table 13. device geometry definition addresses data description 27h 0018h device size = 2 n byte 28h 29h 0001h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 0000h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 0003h number of erase block regions within device 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 1 information (refer to the cfi specification or cfi publication 100) 31h 32h 33h 34h 00fdh 0000h 0000h 0001h erase block region 2 information (refer to the cfi specification or cfi publication 100) 35h 36h 37h 38h 0007h 0000h 0020h 0000h erase block region 3 information (refer to the cfi specification or cfi publication 100) 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h erase block region 4 information (refer to the cfi specification or cfi publication 100)
december 16, 2003 am49pdl127bh/am49pdl129bh 45 advance information table 14. primary vendor-specific extended query addresses data description 40h 41h 42h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 0031h major version number, ascii (reflects modifications to the silicon) 44h 0033h minor version number, ascii (reflects modifications to the cfi table) 45h 000ch address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 0007h sector protect/unprotect scheme 01 =29f040 mode, 02 = 29f016 mode, 03 = 29f400, 04 = 29lv800 mode 4ah 00e7h simultaneous operation 00 = not supported, x = number of sectors excluding bank 1 4bh 0000h burst mode type 00 = not supported, 01 = supported 4ch 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 0085h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 0095h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 0001h top/bottom boot sector flag 00h = uniform device, 02h = bottom boot device, 03h = top boot device, 04h = both top and bottom 50h 0001h program suspend 0 = not supported, 1 = supported 57h 0004h bank organization 00 = data at 4ah is zero, x = number of banks 58h 0027h bank 1 region information x = number of sectors in bank 1 59h 0060h bank 2 region information x = number of sectors in bank 2 5ah 0060h bank 3 region information x = number of sectors in bank 3 5bh 0027h bank 4 region information x = number of sectors in bank 4
46 am49pdl127bh/am49pdl129bh december 16, 2003 advance information command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 15 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence may place the device in an unknown state. a reset com- mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#f1/ce#f2 (pdl129h only), whichever happens later. all data is latched on the rising edge of we# or ce#f1/ce#f2 (pdl129h only), whichever happens first. refer to the flash ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. each bank is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. the system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device out- puts status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same excep- tion. see the erase suspend/erase resume com- mands section for more information. the system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the mcp device bus operations section for more informa- tion. the read-only operations ? am29pdl127h and read-only operations ? am29pdl129h tables pro- vide the read parameters, and figure 14 shows the timing diagram. reset command writing the reset command resets the banks to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the bank to which the sys- tem was writing to the read mode. once erasure be- gins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the bank to which the system was writing to the read mode. if the program command sequence is written to a bank that is in the erase suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if a bank entered the autoselect mode while in the erase sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. if dq5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in erase suspend). autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. the autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. the autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the bank address and the au- toselect command. the bank then enters the autose- lect mode. the system may read any number of autoselect codes without reinitiating the command se- quence. table 15 shows the address and data requirements. to determine sector protection information, the system must write to the appropriate bank address (ba) and sector address (sa). ta bl e 4 shows the address range and bank number associated with each sector. the system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in erase suspend).
december 16, 2003 am49pdl127bh/am49pdl129bh 47 advance information enter secsi? sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing a random, eight wo rd electronic serial num- ber (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector command sequence returns the de- vice to normal operation. the secsi sector is not ac- cessible when the device is executing an embedded program or embedded erase algorithm. table 15 shows the address and data requirements for both command sequences. see also ?secsi? (secured sili- con) sector flash memory region? for further informa- tion. note that the acc function and unlock bypass modes are not available when the secsi sector is en- abled. word program command sequence programming is a four-bus-cycle operation. the pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program al- gorithm. the system is not required to provide further controls or timings. the device automatically provides internally generated program pulses and verifies the programmed cell margin. table 15 shows the address and data requirements for the program command se- quence. when the embedded program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7, dq6, or ry/by#. refer to the write operation status section for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program operation. note that the secsi sector, autoselect, and cfi functions are unavailable when the secsi sector is enabled. the program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause that bank to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was success- ful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.? unlock bypass command sequence the unlock bypass feature allows the system to pro- gram data to a bank faster than using the standard program command sequence. the unlock bypass command sequence is initiated by first writing two un- lock cycles. this is followed by a third write cycle con- taining the unlock bypass command, 20h. that bank then enters the unlock bypass mode. a two-cycle un- lock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program com- mand, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 15 shows the requirements for the command sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device automatically en- ters the unlock bypass mode. the system may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh any operation other than accelerated programming, or device dam- age may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. figure 5 illustrates the algorithm for the program oper- ation. refer to the erase and program operations table in the ac characteristics section for parameters, and figures 17 and 18 for timing diagrams.
48 am49pdl127bh/am49pdl129bh december 16, 2003 advance information figure 5. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 15 shows the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status sec- tion for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset im- mediately terminates the erase operation. note that the secsi sector, autoselect, and cfi functions are un- available when the secsi sector is enabled. if that oc- curs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 15 shows the ad- dress and data requirements for the sector erase com- mand sequence. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any command other than sector erase or erase suspend during the time-out period resets that bank to the read mode. note that the secsi sec- tor, autoselect, and cfi functions are unavailable when the secsi sector is enabled. the system must rewrite the command sequence and any additional ad- dresses and commands. the system can monitor dq3 to determine if the sec- tor erase timer has timed out (see the section on dq3: sector erase timer). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing bank. the system can de- termine the status of the erase operation by reading start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress note: see table 15 for program command sequence.
december 16, 2003 am49pdl127bh/am49pdl129bh 49 advance information dq7, dq6, dq2, or ry/by# in the erasing bank. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. figure 6 illustrates the algorithm for the erase opera- tion. refer to the erase and program operations ta- bles in the ac characteristics section for parameters, and figure 19 section for timing diagrams. figure 6. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. the bank address is required when writing this command. this command is valid only during the sector erase operation, including the 80 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written dur- ing the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a max- imum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. addresses are ?don?t-cares? when writing the erase suspend command. after the erase operation has been suspended, the bank enters the erase-suspend-read mode. the sys- tem can read data from or program data to any sector not selected for erasure. (the device ?erase sus- pends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for infor- mation on these status bits. after an erase-suspended program operation is com- plete, the bank returns to the erase-suspend-read mode. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect command sequence. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the au- toselect mode, the device reverts to the erase sus- pend mode, and is ready for another valid operation. refer to the autoselect command sequence sections for details. to resume the sector erase operation, the system must write the erase resume command (address bits are don?t care). the bank address of the erase-sus- pended bank is required when writing this command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing. password program command the password program command permits program- ming the password that is used as part of the hard- ware protection scheme. the actual password is 64-bits long. four password program commands are required to program the password. the system must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. there are no pro- visions for entering the 2-cycle unlock cycle, the pass- start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 15 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
50 am49pdl127bh/am49pdl129bh december 16, 2003 advance information word program command, and all the password data. there is no special addressing order required for pro- gramming the password. also, when the password is undergoing programming, simultaneous operation is disabled. read operations to any memory location will return the programming status. once programming is complete, the user must issue a read/reset com- mand to return the device to normal operation. once the password is written and verified, the password mode locking bit must be set in order to prevent verifi- cation. the password program command is only ca- pable of programming ?0?s. programming a ?1? after a cell is programmed as a ?0? results in a time-out by the embedded program algorithm? with the cell remain- ing as a ?0?. the password is all ones when shipped from the factory. all 64-bit password combinations are valid as a password. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device will al- ways drive all f?s onto the dq data bus. the password verify command is permitted if the secsi sector is enabled. also, the device will not oper- ate in simultaneous operation when the password verify command is executed. only the password is re- turned regardless of the bank address. the lower two address bits (a1-a0) are valid during the password verify. writing the read/reset command returns the device back to normal operation. password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, which prevents further verifies or updates to the password. once programmed, the password protection mode locking bit cannot be erased! if the password protection mode locking bit is verified as program without margin, the password protection mode locking bit program command can be executed to improve the program margin. once the password protection mode locking bit is programmed, the per- sistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. exiting the mode locking bit program command is accomplished by writing the read/reset command. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode locking bit, which prevents the pass- word mode locking bit from ever being programmed. if the persistent sector protection mode locking bit is verified as programmed without margin, the persistent sector protection mode locking bit program com- mand should be reissued to improve program margin. by disabling the program circuitry of the password mode locking bit, the device is forced to remain in the persistent sector protection mode of operation, once this bit is set. exiting the persistent protection mode locking bit program command is accomplished by writing the read/reset command. secsi sector protection bit program command the secsi sector protection bit program command programs the secsi sector protection bit, which pre- vents the secsi sector memory from being cleared. if the secsi sector protection bit is verified as pro- grammed without margin, the secsi sector protection bit program command should be reissued to improve program margin. exiting the v cc -level secsi sector protection bit program command is accomplished by writing the read/reset command. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully exe- cuted. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared un- less the device is taken through a power-on clear or the password unlock command is executed. upon set- ting the ppb lock bit, the ppbs are latched into the dybs. if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycle. exiting the ppb lock bit set command is accomplished by writing the read/reset command (only in the persistent protection mode). dyb write command the dyb write command is used to set or clear a dyb for a given sector. the high order address bits a22?a12 for pdl127 and a21?a12 for pdl129h are issued at the same time as the code 01h or 00h on dq7-dq0. all other dq data bus pins are ignored dur- ing the data write cycle. the dybs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dybs are cleared at power-up or hard- ware reset. exiting the dyb write command is accom- plished by writing the read/reset command. password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become ac-
december 16, 2003 am49pdl127bh/am49pdl129bh 51 advance information cessible for modification. the exact password must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 s at a time to prevent a hacker from running through all 64-bit combinations in an attempt to correctly match a password. if the command is issued before the 2 s execution window for each portion of the unlock, the command will be ignored. once the password unlock command is entered, the ry/by# indicates that the device is busy. approxi- mately 1 s is required for each portion of the unlock. once the first portion of the password unlock com- pletes (ry/by# is not low or dq6 does not toggle when read), the next part of the password is written. the system must thus monitor ry/by# or the status bits to confirm when to write the next portion of the password. seven cycles are required to successfully clear the ppb lock bit. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually pro- grammed (but is bulk erased with the other ppbs). the specific sector address (a21?a12) are written at the same time as the program command 60h with a6 = 0. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command will not execute and the command will time-out without programming the ppb. after programming a ppb, two additional cycles are needed to determine whether the ppb has been pro- grammed with margin. if the ppb has been pro- grammed without margin, the program command should be reissued to improve the program margin. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs be- yond 100 cycles is not guaranteed. the ppb program command does not follow the em- bedded program algorithm. all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually eras- ing a specific ppb. unlike the ppb program, no spe- cific sector address is required. however, when the ppb erase command is written all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the com- mand will time-out without erasing the ppbs. after erasing the ppbs, two additional cycles are needed to determine whether the ppb has been erased with margin. if the ppbs has been erased without margin, the erase command should be reissued to improve the program margin. it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-era- sure may occur making it difficult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. dyb write command the dyb write command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sector is pro- tected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, remov- ing power or resetting the device will clear the dybs. the bank address is latched when the command is written. ppb lock bit set command the ppb lock bit set command is used for setting the dyb, which is a volatile bit that is cleared at reset. there is one dyb per sector. if the ppb is set, the sec- tor is protected regardless of the value of the dyb. if the ppb is cleared, setting the dyb to a 1 protects the sector from programs or erases. since this is a volatile bit, removing power or resetting the device will clear the dybs. the bank address is latched when the com- mand is written. ppb status command the programming of the ppb for a given sector can be verified by writing a ppb status verify command to the device. ppb lock bit status command the programming of the ppb lock bit for a given sec- tor can be verified by writing a ppb lock bit status ver- ify command to the device. sector protection status command the programming of either the ppb or dyb for a given sector or sector group can be verified by writing a sec- tor protection status command to the device. note that there is no single command to independently verify the programming of a dyb for a given sector group.
52 am49pdl127bh/am49pdl129bh december 16, 2003 advance information command definitions tables legend: ba = address of bank switching to autoselect mode, bypass mode, or erase operation. determined by a22:a20, (a21:a20 for pdl129) see ta b l e s 4 and 7 for more detail. pa = program address (a22:a0) (a21:a0 for pdl129). addresses latch on falling edge of we# or ce#f1/ce#f2 (pdl129 only) pulse, whichever happens later. pd = program data (dq15:dq0) written to location pa. data latches on rising edge of we# or ce#f1/ce#f2 (pdl129 only) pulse, whichever happens first. ra = read address (a22:a0) (a21:a0 for pdl129). rd = read data (dq15:dq0) from location ra. sa = sector address (a22:a12) (a21:a12 for pdl129) for verifying (in autoselect mode) or erasing. wd = write data. see ?configuration register? definition for specific write data. data latched on rising edge of we#. x = don?t care notes: 1. see ta bl e 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. no unlock or command cycles required when bank is reading array data. 6. the reset command is required to return to reading array (or to erase-suspend-read mode if previously in erase suspend) when bank is in autoselect mode, or if dq5 goes high (while bank is providing status information). 7. fourth cycle of autoselect command sequence is a read cycle. system must provide bank address to obtain manufacturer id or device id information. see autoselect command sequence section for more information. 8. the data is c0h for factory or customer locked and 80h for factory locked. 9. the data is 00h for an unprotected sector group and 01h for a protected sector group. 10. device id must be read across cycles 4, 5, and 6. data is 20 for am29pdl127h and 21 for am29pdl129h. 11. system may read and program in non-erasing sectors, or enter autoselect mode, when in program/erase suspend mode. program/erase suspend command is valid only during a sector erase operation, and requires bank address. 12. program/erase resume command is valid only during erase suspend mode, and requires bank address. 13. command is valid when device is ready to read array data or when device is in autoselect mode. 14. wp#/acc must be at v id during the entire operation of command. 15. unlock bypass entry command is required prior to any unlock bypass operation. unlock bypass reset command is required to return to the reading array. table 15. memory array command definitions command (notes) cycles bus cycles (notes 1?4) addr data addr data addr data addr data addr data addr data read (5) 1 ra rd reset (6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 (ba)x00 01 device id (10) 6 555 aa 2aa 55 555 90 (ba)x01 7e (ba)x0e (note 10) (ba)x0f 00 secsi sector factory protect (8) 4 555 aa 2aa 55 555 90 x03 (see note 8) sector group protect verify (9) 4 555 aaa 2aa 55 555 90 (sa)x02 xx00/ xx01 program 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (11) 1 ba b0 program/erase resume (12) 1 ba 30 cfi query (13) 1 55 98 accelerated program (15) 2 xx a0 pa pd unlock bypass entry (15) 3 555 aa 2aa 55 555 20 unlock bypass program (15) 2 xx a0 pa pd unlock bypass erase (15) 2 xx 80 xx 10 unlock bypass cfi (13, 15) 1 xx 98 unlock bypass reset (15) 2 xxx 90 xxx 00
december 16, 2003 am49pdl127bh/am49pdl129bh 53 advance information legend: dyb = dynamic protection bit ow = address (a7:a0) is (00011010) pd[3:0] = password data (1 of 4 portions) ppb = persistent protection bit pwa = password address. a1:a0 selects portion of password. pwd = password data being verified. pl = password protection mode lock address (a7:a0) is (00001010) rd(0) = read data dq0 for protection indicator bit. rd(1) = read data dq1 for ppb lock status. sa = sector address where security command applies. address bits a21:a12 uniquely select any sector. sl = persistent protection mode lock address (a7:a0) is (00010010) wp = ppb address (a7:a0) is (00000010) (note 16) x = don?t care ppmlb = password protection mode locking bit spmlb = persistent protection mode locking bit 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells in table denote read cycles. all other cycles are write operations. 4. during unlock and command cycles, when lower address bits are 555 or 2aah as shown in table, address bits higher than a11 (except where ba is required) and data bits higher than dq7 are don?t cares. 5. the reset command returns device to reading array. 6. cycle 4 programs the addressed locking bit. cycles 5 and 6 validate bit has been fully programmed when dq0 = 1. if dq0 = 0 in cycle 6, program command must be issued and verified again. 7. data is latched on the rising edge of we#. 8. entire command sequence must be entered for each portion of password. 9. command sequence returns ffh if ppmlb is set. 10. the password is written over four consecutive cycles, at addresses 0-3. 11. a 2 s timeout is required between any two portions of password. 12. a 100 s timeout is required between cycles 4 and 5. 13. a 1.2 ms timeout is required between cycles 4 and 5. 14. cycle 4 erases all ppbs. cycles 5 and 6 validate bits have been fully erased when dq0 = 0. if dq0 = 1 in cycle 6, erase command must be issued and verified again. before issuing erase command, all ppbs should be programmed to prevent ppb overerasure. 15. dq1 = 1 if ppb locked, 0 if unlocked. 16. for pdl128g and pdl640g, the wp address is 0111010. the ep address (ppb erase address) is 1111010. 17. following the final cycle of the command sequence, the user must write the first three cycles of the autoselect command and then write a reset command. 18. if checking the dyb status of sectors in multiple banks, the user must follow note 17 before crossing a bank boundary. table 16. sector protection command definitions command (notes) cycles bus cycles (notes 1-4) addr data addr data addr data addr data addr data addr data addr data reset 1 xxx f0 secsi sector entry 3 555 aa 2aa 55 555 88 secsi sector exit 4 555 aa 2aa 55 555 90 xx 00 secsi protection bit program (5, 6) 6 555 aa 2aa 55 555 60 ow 68 ow 48 ow rd(0) secsi protection bit status 5 555 aa 2aa 55 555 60 ow 48 ow rd(0) password program (5, 7, 8) 4 555 aa 2aa 55 555 38 xx[0-3] pd[0-3] password verify (6, 8, 9) 4 555 aa 2aa 55 555 c8 pwa[0-3] pwd[0-3] password unlock (7, 10, 11) 7 555 aa 2aa 55 555 28 pwa[0] pwd[0] pwa[1] pwd[1] pwa[2] pwd[2] pwa[3] pwd[3] ppb program (5, 6, 12, 17) 6 555 aa 2aa 55 555 60 (sa)wp 68 (sa)wp 48 (sa)wp rd(0) ppb status 5 555 aa 2aa 55 555 60 (sa)wp 48 (sa)wp rd (0) all ppb erase (5, 6, 13, 14) 6 555 aa 2aa 55 555 60 wp 60 (sa) 40 (sa)wp rd(0) ppb lock bit set (17) 3 555 aa 2aa 55 555 78 ppb lock bit status (15) 4 555 aa 2aa 55 555 58 sa rd(1) dyb write (7) 4 555 aa 2aa 55 555 48 sa x1 dyb erase (7) 4 555 aa 2aa 55 555 48 sa x0 dyb status (6, 18) 4 555 aa 2aa 55 555 58 sa rd(0) ppmlb program (5, 6, 12) 6 555 aa 2aa 55 555 60 pl 68 pl 48 pl rd(0) ppmlb status (5) 5 555 aa 2aa 55 555 60 pl 48 pl rd(0) spmlb program (5, 6, 12) 6 555 aa 2aa 55 555 60 sl 68 sl 48 sl rd(0) spmlb status (5) 5 555 aa 2aa 55 555 60 sl 48 sl rd(0)
54 am49pdl127bh/am49pdl129bh december 16, 2003 advance information write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 17 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is com- plete or in progress. the device also provides a hard- ware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether a bank is in erase sus- pend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device out- puts on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is ac- tive for approximately 1 s, then that bank returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the bank enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# poll- ing on dq7 is active for approximately 400 s, then the bank returns to the read mode. if not all selected sec- tors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. however, if the sys- tem reads dq7 at an address within a protected sector, the status may not be valid. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq15?dq0 on the following read cycles. just prior to the completion of an embedded program or erase op- eration, dq7 may change asynchronously with dq15?dq0 while output enable (oe#) is asserted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has com- pleted the program or erase operation and dq7 has valid data, the data outputs on dq15?dq0 may be still invalid. valid data on dq15?dq0 will appear on suc- cessive read cycles. table 17 shows the outputs for data# polling on dq7. figure 7 shows the data# polling algorithm. figure 7 in the flash ac characteristics section shows the data# polling timing diagram. figure 7. data# polling algorithm dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7?dq0 addr = va read dq7?dq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
december 16, 2003 am49pdl127bh/am49pdl129bh 55 advance information ry/by#: ready/busy# the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, sev- eral ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or one of the banks is in the erase-sus- pend-read mode. table 17 shows the outputs for ry/by#. dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or com- plete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any ad- dress, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce#f1 to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 400 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase sus- pend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# poll- ing). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 17 shows the outputs for toggle bit i on dq6. figure 8 shows the toggle bit algorithm. figure 22 in the ?flash ac characteristics? section shows the tog- gle bit timing diagrams. figure 23 shows the differ- ences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. figure 8. toggle bit algorithm start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete toggle bit = toggle? read byte twice (dq7?dq0) address = va read byte (dq7?dq0) address =va read byte (dq7?dq0) address =va note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
56 am49pdl127bh/am49pdl129bh december 16, 2003 advance information dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (the system may use either oe# or ce#f1 to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for era- sure. thus, both status bits are required for sector and mode information. refer to table 17 to compare out- puts for dq2 and dq6. figure 8 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsection. figure 22 shows the toggle bit timing diagram. figure 23 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 8 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7?dq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of figure 8). dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously pro- grammed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the operation, and when the timing limit has been exceeded, dq5 produces a ?1.? under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all fur- ther commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept additional sector erase commands. to ensure the command has been accepted, the sys- tem software should check the status of dq3 prior to and following each subsequent sector erase com- mand. if dq3 is high on the second status check, the last command might not have been accepted. table 17 shows the status of dq3 relative to the other status bits.
december 16, 2003 am49pdl127bh/am49pdl129bh 57 advance information table 17. write operation status notes: 1. dq5 switches to ?1? when an embedded program or embedded erase operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. when reading write operation status bits, the system must always provide the bank address where the embedded algorithm is in progress. the device outputs array data if the system addresses a non-busy bank. status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase suspend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
58 am49pdl127bh/am49pdl129bh december 16, 2003 advance information absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?55 c to +125 c ambient temperature with power applied. . . . . . . . . . . . . . . ?40 c to +85 c voltage with respect to ground v cc f, v cc s (note 1) . . . . . . . . . . . . ?0.5 v to +4.0 v reset# (note 2) . . . . . . . . . . . .?0.5 v to +12.5 v wp#/acc . . . . . . . . . . . . . . . . . . ?0.5 v to +10.5 v all other pins (note 1) . . . . . . ?0.5 v to v cc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc +0.5 v. see figure 8. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 9. 2. minimum dc input voltage on pins reset#, and wp#/acc is ?0.5 v. during voltage transitions, wp#/acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8. maximum dc input voltage on pin reset# is +12.5 v which may overshoot to +14.0 v for periods up to 20 ns. maximum dc input voltage on wp#/acc is +9.5 v which may overshoot to +12.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. figure 9. maximum negative overshoot waveform figure 10. maximum positive overshoot waveform operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c v cc f/v cc s supply voltages v cc f/v cc s for standard voltage range . . 2.7 v to 3.3 v operating ranges define those limits between which the functionality of the device is guaranteed. esd immunity spansion flash memory multi-chip products (mcps) may contain component devices that are developed by fasl llc (?spansion components?) and component devices that are developed by a third party (?third-party components?). spansion components are tested and guaranteed to the esd immunity levels listed in the corresponding spansion flash memory qualification database. third-party components are neither tested nor guaran- teed by fasl llc for esd immunity. however, esd test results for third-party components may be avail- able from the component manufacturer. component manufacturer contact information is listed in the span- sion mcp qualification report, when available. the spansion flash memory qualification database and spansion mcp qualification report are available from amd and fujitsu sales offices. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
december 16, 2003 am49pdl127bh/am49pdl129bh 59 advance information dc characteristics cmos compatible notes: 1. valid ce#f1/ce#f2 conditions (pdl129 only): (ce#f1= v il , ce#f2= v ih ) or (ce#f1= v ih , ce#f2= v il ) 2. the i cc current listed is typically less than 5 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v ccmax . 4. i cc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 150 ns. typical sleep mode current is 1 a. 6. not 100% tested. parameter symbol parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, oe#, reset# input load current v cc = v cc max ; v id = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; v id = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , oe# = v ih v cc = v cc max 1.0 a i cc1 v cc active read current (notes 1, 2, 3) oe# = v ih , v cc = v cc max (note 1) 5 mhz 20 30 ma 10 mhz 45 55 i cc2 v cc active write current (notes 1, 3, 4) oe# = v ih , we# = v il 15 25 ma i cc3 v cc standby current (note 3) ce#f1, ce#f2 (pdl129 only), reset#, wp/acc# = v io 0.3 v 15a i cc4 v cc reset current (note 3) reset# = v ss 0.3 v, ce# = v ss 15a i cc5 automatic sleep mode (notes 3, 5) v ih = v io 0.3 v; v il = v ss 0.3 v, ce# = v ss 15a i cc6 v cc active read-while-program current (notes 1, 2, 3) oe# = v ih word 21 45 ma i cc7 v cc active read-while-erase current (notes 1, 2, 3) oe# = v ih word 21 45 ma i cc8 v cc active program-while-erase- suspended current (notes 1, 3, 6) oe# = v ih 17 25 ma v il input low voltage v io = 2.7?3.6 v ?0.5 0.8 v v ih input high voltage v io = 2.7?3.6 v 2.0 v cc +0.3 v v hh voltage for acc program acceleration v cc = 3.0 v 10% 8.5 9.5 v v id voltage for autoselect and temporary sector unprotect v cc = 3.0 v 10% 11.5 12.5 v v ol output low voltage i ol = 2.0 ma, v cc = v cc min 0.4 v v oh output high voltage i oh = ?2.0 ma, v cc = v cc min 2.4 v v lko low v cc lock-out voltage (note 6) 2.3 2.5 v
60 am49pdl127bh/am49pdl129bh december 16, 2003 advance information psram dc & operating characteristics notes: 1. v cc ?1.0 v for a 10 ns pulse width. 2. v cc +1.0 v for a 10 ns pulse width. parameter symbol parameter description test conditions min typ max unit i li input leakage current v in = v ss to v cc ?1.0 1.0 a i lo output leakage current ce#1ps = v ih , ce2ps = v il or oe# = v ih or we# = v il, v io = v ss to v cc ?1.0 1.0 a i cc1 s operating current cycle time = min., i io = 0 ma, 100% duty, ce#1ps = v il , ce#2ps = v ih , v in = v il = v ih , t rc = min 40 ma i cc2 s page access operating current cycle time = min., i io = 0 ma, 100% duty, ce#1ps = v il , ce#2ps = v ih , v in = v il = v ih , t pc = min 25 ma v ol output low voltage i ol = 1.0 ma 0.4 v v oh output high voltage i oh = ?0.5 ma 2 v i sb standby current (cmos) ce#f1 = v ccs ?0.2 v, ce2 = v ccs = 0.2 v 70 a i dsb deep power-down standby ce2 = 0.2 v 5 a v il input low voltage ?0.3 (note 1) 0.4 v v ih input high voltage 2.4 v cc + 0.3 (note 2) v
december 16, 2003 am49pdl127bh/am49pdl129bh 61 advance information test conditions table 18. test specifications key to switching waveforms 2.7 k ? c l 6.2 k ? 3.3 v device under te s t note: diodes are in3064 or equivalent figure 11. test setup test condition 66, 85 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0?3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v ks000010-pal waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input figure 12. input waveforms and measurement levels
62 am49pdl127bh/am49pdl129bh december 16, 2003 advance information psram ac characteristics ce#1ps timing figure 13. timing diagram for alternating between pseudo sram and flash parameter description test setup all speeds unit jedec std ?t ccr ce#1ps recover time ? min 0 ns ce#1ps t ccr t ccr ce2ps
december 16, 2003 am49pdl127bh/am49pdl129bh 63 advance information flash ac characteristics read-only operations ? am29pdl127h notes: 1. not 100% tested. 2. see figure 11 and table 18 for test specifications 3. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . read-only operations ? am29pdl129h notes: 1. not 100% tested. 2. see figure 11 and table 18 for test specifications 3. valid ce#f1/ce#f2 conditions: (ce#f1= v il , ce#f2= v ih ) or (ce#f1= v ih , ce#f2=v il ). 4. valid ce#f1/ce#f2 transitions: (ce#f1= ce#f2= v ih ) to (ce#f1= v il , ce#f2=v ih ) or (ce#f1= v ih , ce#f2=v il ). 5. measurements performed by placing a 50 ohm termination on the data pin with a bias of v cc /2. the time from oe# high to the data bus driven to v cc /2 is taken as t df . 6. valid ce#f1/ce#f2 transitions: (ce#f1= v il , ce#f2= v ih ) or (ce#f1= v ih , ce#f2=v il ) to (ce#f1= ce#f2= v ih ). parameter description test setup speed options jedec std. 66 85 unit t avav t rc read cycle time (note 1) min 65 85 ns t avqv t acc address to output delay ce#f1, oe# = v il max 65 85 ns t elqv t ce chip enable to output delay oe# = v il max 65 85 ns t pac c page access time max 25 30 ns t glqv t oe output enable to output delay max 25 30 ns t ehqz t df chip enable to output high z (note 1, 3) max 16 ns t ghqz t df output enable to output high z (notes 1, 3) max 16 ns t axqx t oh output hold time from addresses, ce#f1 or oe#, whichever occurs first (notes 3) min 5 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns parameter description test setup speed options jedec std. 66 85 unit t avav t rc read cycle time (note 1) min 65 85 ns t avqv t acc address to output delay (note 3) ce#f1, oe# = v il max 65 85 ns t elqv t ce chip enable to output delay (note 4) oe# = v il max 65 85 ns t pac c page access time max 25 30 ns t glqv t oe output enable to output delay max 25 30 ns t ehqz t df chip enable to output high z (notes 1, 5, 6) max 16 ns t ghqz t df output enable to output high z (notes 1, 5) max 16 ns t axqx t oh output hold time from addresses, ce#f1/ce#f2 or oe#, whichever occurs first (notes 5, 6) min 5 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns
64 am49pdl127bh/am49pdl129bh december 16, 2003 advance information flash ac characteristics figure 15. page read operation timings notes: during ce#f1 transitions, ce#f2= v ih ; during ce#f2 transitions, ce#f1= v ih t oh t ce outputs we# addresses ce#f1 oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df or ce#f2 (pdl 129 only) figure 14. read operation timings addresses ce# f1 or ce#f2 (pdl129 only) oe# a2 - a0 data same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
december 16, 2003 am49pdl127bh/am49pdl129bh 65 advance information flash ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options unit jedec std t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s t rb ry/by# recovery time min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#f1, ce#f2 (pdl129 only), oe# t rh ce#f1, ce#f2 (pdl129 only), oe# reset timings during embedded algorithms reset# t rp t rb figure 16. reset timings
66 am49pdl127bh/am49pdl129bh december 16, 2003 advance information flash ac characteristics erase and program operations notes: 1. not 100% tested. 2. see the ?flash erase and programming performance? section for more information. parameter speed jedec std description 66 85 unit t avav t wc write cycle time (note 1) min 65 85 ns t avwl t as address setup time min 05 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 35 ns t aht address hold time from ce#1f or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 30 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 10 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time (ce#f1 to we#) min 0 ns t elwl t cs ce#f1 setup time min 0 ns t ehwh t wh we# hold time (ce#f1 to we#) min 0 ns t wheh t ch ce#f1 hold time min 0 ns t wlwh t wp write pulse width min 40 ns t whdl t wph write pulse width high min 25 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) word typ 6 s t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vcs v cc setup time (note 1) min 50 s t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns
december 16, 2003 am49pdl127bh/am49pdl129bh 67 advance information flash ac characteristics oe# we# ce#f1 or ce#f2 (pdl129 only) v cc f data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) ry/by# t rb t busy t ch pa n otes: 1 . pa = program address, pd = program data, d out is the true data at the program address. 2 . illustration shows device in word mode. 3 . for pdl129 during ce#f1 transitions the other ce#f1 pin = v ih. figure 17. program operation timings wp#/acc t vhh v hh v il or v ih v il or v ih t vhh figure 18. accelerated program timing diagram
68 am49pdl127bh/am49pdl129bh december 16, 2003 advance information flash ac characteristics oe# ce#f1 or ce#f2 (pdl129 only) addresses v cc f we# data 2aah sadd t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy notes: 1. sadd = sector address (for sector erase), va = valid address for reading status data (see ?flash write operation status?. 2 . for pdl129 during ce#f1 transitions the other ce#f1 pin = v ih . figure 19. chip/sector erase operation timings
december 16, 2003 am49pdl127bh/am49pdl129bh 69 advance information flash ac characteristics oe# we# addresses t oh data valid in valid in valid pa valid ra t wc t wph t ah t wp t ds t dh t rc t ce valid out t oe t acc t oeh t ghwl t df valid in ce#f controlled write cycles we# controlled write cycle valid pa valid pa t cp t cph t wc t wc read cycle t sr/w ce#f1 or ce#f2 (pdl129 only) figure 20. back-to-back read/write cycle timings we# ce#f1 or ce#f2 (pdl129 only) oe# high z t oe high z dq7 dq6?dq0 ry/by# t busy complement tr u e addresses va t oeh t ce t ch t oh t df va va status data complement status data tr u e valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 21. data# polling timings (during embedded algorithms)
70 am49pdl127bh/am49pdl129bh december 16, 2003 advance information flash ac characteristics oe# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6/dq2 valid data valid status valid status valid status ry/by# ce#f1 or ce#f2 (pdl129 only) note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 22. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce#f1 to toggle dq2 and dq6. figure 23. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
december 16, 2003 am49pdl127bh/am49pdl129bh 71 advance information flash ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 s t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce#f1 or ce#f2 (pdl129 only) we# ry/by# t vidr t rsp program or erase command sequence t rrb figure 24. temporary sector unprotect timing diagram
72 am49pdl127bh/am49pdl129bh december 16, 2003 advance information flash ac characteristics sector/sector block protect: 150 s, sector/sector block unprot ect: 15 ms 1 s reset# sadd, a6, a1, a0 data ce#f1 or ce#f1(pdl129 only) we# oe# 60h 60h 40h valid* valid* valid* status sector/sector block protect or unprotect verify v id v ih 1. for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0, sadd = sector address. 2. for pdl129 during ce#f1 transitions the other ce#f1 pin = v ih . figure 25. sector/sector block protect and unprotect timing diagram
december 16, 2003 am49pdl127bh/am49pdl129bh 73 advance information flash ac characteristics alternate ce#f1 controlled erase and program operations notes: 1. not 100% tested. 2. see the ?flash erase and programming performance? section for more information. parameter speed jedec std. description 66 85 unit t avav t wc write cycle time (note 1) min 65 85 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 35 ns t dveh t ds data setup time min 30 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce#f1 pulse width min 40 ns t ehel t cph ce#f1 pulse width high min 25 ns t whwh1 t whwh1 word programming operation (note 2) ty p 6 s t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) ty p 4 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.4 sec
74 am49pdl127bh/am49pdl129bh december 16, 2003 advance information flash ac characteristics t ghel t ws oe# ce#f1 or ce#f2 (pdl129 only) we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 ry/by# t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sadd for sector erase 555 for chip erase t busy notes: 1. figure indicates last two bus cycles of a program or erase operation. 2. pa = program address, sadd = sector address, pd = program data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. figure 26. flash alternate ce#f1 controlled write (erase/progra m) operation timings
december 16, 2003 am49pdl127bh/am49pdl129bh 75 advance information psram ac characteristics read cycle notes: 1. t od, t odo , t bd , and t odw are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. if ce#, lb#, or ub# goes low at the same time or before we# goes high, the outputs will remain at high impedance. 3. if ce#, lb#, or ub# goes low at the same time or after we# goes low, the outputs will remain at high impedance. figure 27. pseudo sram read cycle parameter symbol description speed unit 66 85 t rc read cycle time min 70 85 ns t acc address access time max 70 85 ns t co chip enable access time max 70 85 ns t oe output enable access time max 25 ns t ba data byte control access time max 25 ns t coe chip enable low to output active min 10 ns t oee output enable low to output active min 0 ns t be data byte control high to output active min 0 ns t od chip enable high to output high-z max 20 ns t odo output enable high to output high-z max 20 ns t bd data byte control high to output high-z max 20 ns t oh output data hold from address change min 10 ns t pm page mode time min 70 ns t pc page mode cycle time min 30 ns t aa page mode address access time max 30 ns t oh page output data hold time min 10 ns t rc t acc addresses a0 to a20 ce#1 ce2 oe# we# lb#, ub# d out i/o1 to 16 t co t oh fixed high high-z high-z t oe t ba t od t odo t bd valid data out indeterminate t be t oee t coe
76 am49pdl127bh/am49pdl129bh december 16, 2003 advance information psram ac characteristics read cycle figure 28. page read timing notes: 1. t od, t odo , t bd , and t odw are defined as the time at which the outputs achieve the open circuit condition and are not referenced to output voltage levels. 2. if ce#f1, lb#, or ub# goes low at the same time or before we# goes high, the outputs will remain at high impedance. 3. if ce#f1, lb#, or ub# goes low at the same time or after we# goes low, the outputs will remain at high impedance. addresses a0 to a2 addresses a3 to a20 ce#1 ce2 oe# we# lb#, ub# d out i/o1 to 16 t pm t rc t pc t pc t ba t oe t be t coe t aa t od t co t bd t acc t oee t pc d out d out d out d out t aa t aa t odo t oh t aoh t aoh t aoh fixed high maximum 8 words
december 16, 2003 am49pdl127bh/am49pdl129bh 77 advance information psram ac characteristics write cycle notes: 1. if the device is using the i/os to output data, input signals of reverse polarity must not be applied. 2. if oe# is high during the write cycle, the outputs will remain at high impedance. 3. if ce#1ps, lb# or ub# goes low at the same time or after we# goes low, the outputs will remain at high impedance. 4. if ce#1ps, lb# or ub# goes high at the same time or before we# goes high, the outputs will remain at high impedance. figure 29. pseudo sram write cycle?we# control parameter symbol description speed unit 66 85 t wc write cycle time min 70 85 ns t wp write pulse time min 50 60 ns t cw chip enable to end of write min 60 70 ns t bw data byte control to end of write min 60 70 ns t aw address valid to end of write min 60 70 ns t as address setup time min 0 ns t wr write recovery time min 0 ns t odw we# low to write to output high-z max 20 ns t oew we# high to write to output active min 0 ns t ds data set-up time min 30 t dh data hold from write time min 0 ns t ch ce2 hold time min 300 s t ceh chip enable high pulse width min 10 ns t weh write enable high pulse width min 6 ns t wc t wp t wr t cw t bw valid data in t as t ch t oew addresses a20 to a0 we# ce#1 ce2 lb#, ub# d in dq15 to dq0 d out dq15 to dq0 t odw t ds t dh high-z (note 1) (note 3) (note 4)
78 am49pdl127bh/am49pdl129bh december 16, 2003 advance information psram ac characteristics notes: 1. if the device is using the i/os to output data, input signals of reverse polarity must not be applied. 2. if oe# is high during the write cycle, the outputs will remain at high impedance. figure 30. pseudo sram write cycle?ce1#s control t wc valid data in t as t ch addresses a20 to a0 ce#1 ce2 we# lb#, ub# d in dq15 to dq0 d out dq15 to dq0 t cw t ds t dh t wp t wr t bw t be t odw t coe high-z high-z (note 1) (note 1)
december 16, 2003 am49pdl127bh/am49pdl129bh 79 advance information psram ac characteristics notes: 1. if the device is using the i/os to output data, input signals of reverse polarity must not be applied. 2. if oe# is high during the write cycle, the outputs will remain at high impedance. figure 31. pseudo sram write cycle? ub#s and lb#s control t wc valid data in addresses a20 to a0 we# ce#1 ce2 ub#, lb# d in dq15 to dq0 d out dq15 to dq0 t ds t wr t wp t cw high-z high-z t ch t dh t as t bw t be t coe t odw
80 am49pdl127bh/am49pdl129bh december 16, 2003 advance information erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. all values are subject to change. 2. under worst case conditions of 90 c, v cc = 2.7 v, 1,000,000 cycles. all values are subject to change. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see tables table 15 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. package pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. flash data retention parameter typ (note 1) max (note 2) unit comments sector erase time 0.4 5 sec excludes 00h programming prior to erasure (note 4) chip erase time 108 sec word program time 7 210 s excludes system level overhead (note 5) accelerated word program time 4 120 s chip program time (note 3) 50 200 sec description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 11 14 pf c out output capacitance v out = 0 12 16 pf c in2 control pin capacitance v in = 0 14 16 pf c in3 wp#/acc pin capacitance v in = 0 17 20 pf parameter description test conditions min unit minimum pattern data retention time 150 c10years 125 c20years
december 16, 2003 am49pdl127bh/am49pdl129bh 81 advance information psram data retention notes: 1. ce1#ps v cc ? 0.2 v, ce2ps v cc ? 0.2 v (ce1#s controlled) or ce2ps 0.2 v (ce2ps controlled). 2. typical values are not 100% tested. psram power on and deep power down figure 32. deep power-down timing note: data cannot be retained during deep power-down standby mode. figure 33. power-on timing parameter symbol parameter description test setup min typ max unit v dr v cc for data retention cs1#ps v cc ? 0.2 v (note 1) 2.7 3.3 v i dr data retention current v cc = 3.0 v, ce1#ps v cc ? 0.2 v (note 1) 1.0 (note 2) 70 a t cs ce2 setup time 0 ns t ch ce2 hold time 300 s t dpd ce2 pulse width 10 ms t chc ce2 hold from ce#1 0 ns t chp ce2 hold from power on 30 s ce#1ps ce#2ps t dpd t ch ce#1ps v dd ce#2ps t chc t chp t ch v dd min
82 am49pdl127bh/am49pdl129bh december 16, 2003 advance information psram address skew figure 34. read address skew note: if multiple invalid address cycles shorter than t rc min occur for a period greater than 10 s, at least one valid address cycle over t rc min is required during that period. figure 35. write address skew note: if multiple invalid address cycles shorter than t wc min occur for a period greater than 10 s, at least one valid address cycle over t wc min , in addition to t wp min , is required during that period. ce#1ps we# address t rc min over 10 s ce#1ps we# address t wp min t wc min over 10 s
december 16, 2003 am49pdl127bh/am49pdl129bh 83 advance information physical dimensions tla073?73-ball fine-pitch grid array 8 x 11.6 mm 10 index mark 73x c 0.15 (2x) (2x) c 0.15 b a 6 b 0.20 c c c 0.15 m c m ab 0.08 d e pin a1 c top view side view corner a2 a1 a 0.08 bottom view 10 9 7 6 8 4 3 1 2 5 a b c d fe g h j k l m ed corner e1 7 se d1 ee sd pin a1 7 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix in the "d" direction. symbol "me" is the ball matrix in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6. dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7. sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9. not used. 10. a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package tla 073 jedec n/a 11.60 mm x 8.00 mm package note symbol min. nom. max. a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.81 --- 0.97 body thickness d 11.60 bsc body size e 8.00 bsc body size d1 8.80 bsc matrix footprint e1 7.20 bsc matrix footprint md 12 matrix size d direction me 10 matrix size e direction n 73 ball count ob 0.33 --- 0.43 ball diameter ee 0.80 bsc ball pitch ed 0.80 bsc ball pitch sd/se 0.40 bsc solder ball placement a2,a3,a4,a5,a6,a7,a8,a9 depopulated solder balls b2,b3,b4,b7,b8,b9 c2,c9,c10,d1,d10,e1,e10 f5,f6,g5,g6,h1,h10,j1,j10 k1,k2,k9,k10,l2,l3,l4,l7,l8,l9 m2,m3,m4,m5,m6,m7,m8,m9 w053003-163814c
84 am49pdl127bh/am49pdl129bh december 16, 2003 advance information revision summary revision a (june 16, 2003) initial release. revision a+1 (july 14, 2003) sector protection selecting a sector protection mode: slightly modified text to improve readability. pin description corrected typo in wp#/acc pin name. flash ac characteristics read-only operation tables (am29pdl127h and am29pdl129h): changed t oe specification for the 66 speed option to 25 ns. sram ac characteristics write cycle table: added t aw , t ceh , and t weh specifica- tions to table. changed t bw minimum time for the 66 speed option to 65 ns. figure 28, pseudo sram write cycle?we# control: added t aw and t weh to figure. figure 29, pseudo sram write cycle?ce#1ps con- trol: added t ceh to figure. revision a+2 (july 21, 2003) dc characteristics zero power flash: deleted selection. revision a+3 (december 16, 2003) lookahead ballout diagram added section and figure. figure 1, in-system sector protection/ sector unprotection algorithms corrected command sequence to indicate writing 68h (for protect) and 48h (for verify) with a7?a0 set to 00011010b. secsi? (secured silicon) sector flash memory region customer-lockable area: added sector protection fig- ure, modified text and changed figure reference in first bullet from figure 1 to figure 3. table 16, sector protection command definitions corrected number of cycles for secsi protection bit status, ppmlb status, and spmlb status from 4 to 5 cycles. for these command sequences, inserted a cycle before the final read cycle (rd0). esd immunity added section. trademarks copyright ? 2003 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are r egistered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .

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